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  • v2.0.1-reset-fanout d0b3a4c969
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    Stable

    mirror released this 2026-04-18 14:49:52 +00:00 | 13 commits to main since this release

    📅 Originally published on GitHub: Sun, 19 Apr 2026 10:37:48 GMT
    🏷️ Git tag created: Sat, 18 Apr 2026 14:49:52 GMT

    AERIS-10 400 MHz Reset Fan-Out Fix + ADAR1000 Channel Indexing

    Hotfix rebuild of the xc7a50t-ftg256-2 production bitstream resolving a 400 MHz clk_dco setup violation (WNS = −0.626 ns) introduced by the reset topology change in v2.0.0-fft2048. Also carries a 1-based channel indexing correction in the ADAR1000 MCU driver (issue #90) that silently wrote the wrong SPI register for channel 1.

    Timing (2026-04-18, commit d0b3a4c)

    Clock Period WNS Failing Endpoints Previous (v2.0.0)
    clk_mmcm_out0 (400 MHz) 2.5 ns +0.020 ns 0 +0.068 ns
    clk_100m (100 MHz) 10.0 ns +0.156 ns 0 +0.156 ns
    clk_120m_dac (120 MHz) 8.333 ns +0.627 ns 0 +0.627 ns
    ft_clkout (60 MHz) 16.667 ns +9.887 ns 0 +9.887 ns
    adc_dco_p (400 MHz) 2.5 ns +0.020 ns 0 +0.920 ns
    Hold (WHS) — +0.035 ns 0 +0.046 ns
    Pulse width (WPWS) — +0.361 ns 0 +0.361 ns
    All constraints met Yes Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util% Previous (v2.0.0)
    LUTs 21,735 32,600 66.67% 21,735 (66.67%)
    Flip-Flops ~14,610 65,200 ~22.41% 14,579 (22.36%)
    BRAM 55.5 75 74.00% 55.5 (74.00%)
    DSP48E1 112 120 93.33% 112 (93.33%)
    F7 Muxes 7,849 16,300 48.15% 7,849 (48.15%)
    F8 Muxes 3,336 8,150 40.93% 3,336 (40.93%)

    FF count increases by ~30 due to reset register replication; dedicated utilization report not generated for this hotfix build.

    What Changed (from v2.0.0-fft2048)

    400 MHz Reset Fan-Out Fix

    • nco_400m_enhanced.v, cic_decimator_4x_enhanced.v, ddc_400m.v: Registered active-high reset reset_h with (* max_fanout=50 *). Prior single-LUT1 inverter drove 700+ loads causing setup violation on the DSP48E1 RSTP path. Vivado now replicates into regional copies (≤50 loads each), meeting setup with +0.020 ns margin.
    • radar_system_top.v: Default USB_MODE changed from 0 (FT601) to 1 (FT2232H). FT601 path remains selectable via explicit parameter override for the 200T premium board.

    MCU — ADAR1000 Channel Indexing (issue #90)

    • ADAR1000_Manager.cpp: Corrected 1-based channel indexing in all phase/gain setters. Prior off-by-one silently addressed the wrong physical SPI register when the caller passed channel 1.
    • test_cross_layer_contract.py: 416-line cross-layer contract test added covering register stride, round-trip correctness for all four setters (adarSetRxPhase, adarSetTxPhase, adarSetRxVgaGain, adarSetTxVgaGain), and caller-site 1-based convention enforcement. Prevents future indexing drift.

    Test Suite

    Layer Tests Status
    Python (GUI) 171 pass, 3 skip Pass
    MCU (C/C++) 88 Pass
    FPGA (iverilog) 27 Pass
    Cross-layer 54 Pass
    Total 340 pass, 3 skip All pass

    Assets

    • xc7a50t-ftg256-prod-2026-04-18.bit — Production bitstream (2,140 KB, program via Vivado/xsdb)
    • xc7a50t-ftg256-prod-timing-2026-04-18.rpt — Post-route timing report
    • xc7a50t-ftg256-prod-2026-04-18.md — Build report and programming instructions

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t (USB_MODE=1, FT2232H)
    • Synth: 152s, Impl: 416s, Bit: ~38s
    Downloads
  • v2.0.0-fft2048 2401f5f89e
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    Stable

    mirror released this 2026-04-16 17:25:05 +00:00 | 37 commits to main since this release

    📅 Originally published on GitHub: Thu, 16 Apr 2026 17:25:56 GMT
    🏷️ Git tag created: Thu, 16 Apr 2026 17:25:05 GMT

    AERIS-10 2048-pt FFT Upgrade + Full Timing Closure

    Complete cross-layer upgrade from 1024-pt to 2048-pt FFT with decimation=4, producing 512 output range bins at 6m spacing (was 64 bins at 24m). All 5 FPGA clock domains timing-closed on xc7a50tftg256-2 after 3 build iterations.

    Timing (Build 19)

    Clock Period WNS Failing Endpoints Previous (v1.1.0)
    clk_mmcm_out0 (400 MHz) 2.5 ns +0.068 ns 0 +0.339 ns
    clk_100m (100 MHz) 10.0 ns +0.156 ns 0 +0.080 ns
    clk_120m_dac (120 MHz) 8.333 ns +0.627 ns 0 —
    ft_clkout (60 MHz) 16.667 ns +9.887 ns 0 —
    adc_dco_p (400 MHz) 2.5 ns +0.920 ns 0 —
    Hold (WHS) — +0.046 ns 0 +0.056 ns
    Pulse width (WPWS) — +0.361 ns 0 +0.361 ns
    All constraints met Yes Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util% Previous (v1.1.0)
    LUTs 21,735 32,600 66.67% 10,252 (31.4%)
    Flip-Flops 14,579 65,200 22.36% 12,820 (19.7%)
    BRAM 55.5 75 74.00% 17.5 (23.3%)
    DSP48E1 112 120 93.33% 112 (93.3%)
    F7 Muxes 7,849 16,300 48.15% —
    F8 Muxes 3,336 8,150 40.93% —

    What Changed (from v1.1.0-agc)

    2048-pt FFT / 512-Bin DSP Pipeline

    • fft_engine.v: 2048-pt FFT with 11 butterfly stages (was 1024/10)
    • range_bin_decimator.v: 4x decimation (was 16x), 512 output bins at 6m spacing
    • doppler_processor.v: 16384-deep Doppler memory (was 2048), 14-bit addressing
    • chirp_memory_loader_param.v: 2-segment loader (was 4), 2048-sample arrays
    • matched_filter_multi_segment.v: 11-bit sample addressing, 2-segment processing
    • radar_receiver_final.v: 9-bit range bin width, sample_addr truncation fix
    • usb_data_interface_ft2232h.v: Bulk per-frame format with Manhattan magnitude
    • radar_params.vh: Single source of truth via include in all RTL modules

    FPGA Timing Closure (Builds 17–19)

    • CFAR pipeline fix (cfar_ca.v): Pre-registered col_buf reads break 15-level mux tree critical path. clk_100m WNS: -0.331ns → +0.156ns
    • CIC reset path fix (cic_decimator_4x_enhanced.v, ddc_400m.v): Eliminated LUT1 inverter on reset fan-out to 8 DSP48E1 RSTB pins. Wired pre-registered reset_400m from DDC. clk_mmcm_out0 WNS: -0.074ns → +0.068ns

    BRAM Inference Fixes (Build 16 → 17)

    • mti_canceller.v: prev_i/q arrays converted from async to sync reset → BRAM inference (saved ~16K fabric FFs)
    • matched_filter_multi_segment.v: overlap_cache sync-only write block → BRAM inference

    Cross-Layer Updates

    • Python GUI: radar_protocol.py bulk frame parser for 512-bin arrays, 6m range scale, 6-bit stream control. Both tkinter and V7 PyQt6 dashboards updated
    • MCU firmware: RadarSettings.cpp max_distance 1536→3072m, map_size updated
    • Golden references: All .hex, .csv, .npy co-sim data regenerated for 2048/512 config
    • Stale cleanup: Deleted dead test classes, stale chirp segment files, dead utility functions

    Test Suite

    Layer Tests Status
    Python (GUI) 172 (tkinter + PyQt6) Pass
    MCU (C/C++) 22 Pass
    FPGA (iverilog) 30 Pass
    Cross-layer 61 Pass
    Total 285 All pass, 0 skip

    Assets

    • radar_system_top_50t.bit — Production bitstream (2,140 KB, program via Vivado/xsdb)
    • 02_timing_summary.rpt — Post-route timing report
    • 04_utilization.rpt — Post-route utilization report

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t
    • Synth: 214s, Impl: 1631s, Bit: 38s
    • Build directives: ExtraNetDelay_high place, 3x AggressiveExplore phys_opt
    Downloads
  • v1.1.0-agc 063fa081fe
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    Stable

    mirror released this 2026-04-13 18:26:24 +00:00 | 64 commits to main since this release

    📅 Originally published on GitHub: Mon, 13 Apr 2026 18:28:11 GMT
    🏷️ Git tag created: Mon, 13 Apr 2026 18:26:24 GMT

    AERIS-10 Hybrid AGC System + FPGA Timing Hardening

    Full hybrid AGC implementation spanning FPGA, STM32, and GUI layers with FPGA timing margin improvements and two rounds of multi-agent code review fixes (20 bugs total).

    Timing

    Metric Value Previous (v1.0.0)
    WNS +0.080 ns +0.088 ns
    WNS (400MHz) +0.339 ns +0.002 ns
    WHS +0.056 ns +0.059 ns
    WPWS +0.361 ns +0.361 ns
    Failing Endpoints 0 0
    All constraints met Yes Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util%
    LUTs 10,252 32,600 31.4%
    Flip-Flops 12,820 65,200 19.7%
    BRAM 17.5 75 23.3%
    DSP48E1 112 120 93.3%
    IOB 82 170 48.2%

    What Changed (from v1.0.0-ft2232h)

    Hybrid AGC System (Phases 1–7)

    • FPGA inner loop: rx_gain_control.v — per-sample gain adjustment with saturation tracking, signed gain range -7 to +7
    • FPGA registers: 0x28–0x2C (enable, target, attack, decay, holdoff) with status readback via status_words[4]
    • STM32 outer loop: AgcOuterLoop class — per-frame ADAR1000 VGA common gain (0–31 dB, 0.5 dB steps) based on FPGA saturation metrics via DIG_5 GPIO
    • STM32 integration: AGC register forwarding, status polling, GUI command routing in main.cpp
    • GUI controls: AGC enable/disable, parameter tuning, status readback in both tkinter and PyQt6 dashboards
    • GUI visualization: Real-time AGC gain/peak/saturation plotting widget with 500ms redraw throttle

    FPGA Timing Hardening (400MHz WNS: +0.002 ns → +0.339 ns)

    • DONT_TOUCH on output BUFG in adc_clk_mmcm.v to prevent AggressiveExplore cascade replication
    • NCO→mixer fabric pipeline registers in ddc_400m.v break critical 1.5 ns route
    • Clock uncertainty reduced 200 ps → 100 ps in adc_clk_mmcm.xdc
    • Updated golden/cosim references for +1 cycle pipeline latency

    Bug Fixes (20 total across two code review rounds)

    • STM32: uint32_t underflow guard in processStartFlag, snprintf buffer safety in getSystemStatusForGUI, early-return error masking in checkSystemHealth, emergency blink delay
    • GUI: opcode set conflict (0x03), V7 diagnostics error count wiring, replay mode label fix, Python 3.12 GIL crash fix
    • FPGA: sign-extension in rx_gain_control.v, FT601 signal comment corrections, self-test timeout comment
    • CI: test_v7.py added to pytest command, ruff lint clean

    Test Suite

    Layer Tests Status
    Python (GUI) 120 (82 tkinter + 38 PyQt6) Pass
    MCU (C/C++) 21 (20 C + 1 C++ w/ 13 AGC sub-tests) Pass
    FPGA (iverilog) 25 (incl. 68 RX gain control checks) Pass
    Cross-layer 29 Pass
    Total 195 All pass

    Assets

    • radar_system_top_50t.bit — Production bitstream (program via Vivado/xsdb)
    • 02_timing_summary.rpt — Post-route timing report
    • 04_utilization.rpt — Post-route utilization report

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t
    • Build directives: ExtraNetDelay_high place, 3x AggressiveExplore phys_opt
    Downloads
  • bitstream-agc-50t-v1 ffba27a10a
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    Pre-Release

    mirror released this 2026-04-13 13:39:11 +00:00 | 69 commits to main since this release

    📅 Originally published on GitHub: Mon, 13 Apr 2026 13:39:56 GMT
    🏷️ Git tag created: Mon, 13 Apr 2026 13:39:11 GMT

    AERIS-10 50T AGC Bitstream — Hybrid AGC + Timing Fix

    Vivado Build 16 bitstream for the XC7A50T-FTG256 production board. Adds hybrid AGC (FPGA inner loop) with 5 new host registers (0x28–0x2C) and a 45x timing margin improvement over the previous build.

    Timing

    Metric Value
    WNS +0.045 ns
    WHS +0.058 ns
    WPWS +0.361 ns
    Failing Endpoints 0
    All constraints met Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util%
    LUTs 10,235 32,600 31.4%
    Flip-Flops 12,729 65,200 19.5%
    BRAM 17.5 75 23.3%
    DSP48E1 112 120 93.3%
    IOB 82 170 48.2%

    What Changed (from v1.0.0-ft2232h)

    • AGC Phase 1: rx_gain_control.v rewritten — per-frame peak/saturation tracking, auto-shift with attack/decay/holdoff, signed gain ±7 (±42 dB)
    • AGC Phase 2: New registers 0x28–0x2C (agc_enable, agc_target, agc_attack, agc_decay, agc_holdoff) in radar_system_top.v
    • AGC Phase 3: status_words[4] carries AGC metrics (gain, peak magnitude, saturation count, enable). DIG_5 GPIO (H11) outputs saturation flag for STM32 outer loop. Both USB interfaces (FT601 + FT2232H) updated.
    • Timing fix: CIC max_fanout 4→16, +200 ps setup uncertainty on 400 MHz domain, ExtraNetDelay_high placement + AggressiveExplore routing
    • GUI Phase 6: AGC opcodes + status parsing in radar_protocol.py. AGC control groups in both tkinter and V7 PyQt dashboards. 11 new AGC tests.
    • Cross-layer: AGC opcodes/defaults/status assertions added. contract_parser.py comment-stripping fix.
    • CI: 157 tests passing (103 Python GUI + 25 FPGA iverilog + 29 cross-layer)

    Assets

    • radar_system_top_50t.bit — Production bitstream (program via Vivado/xsdb)
    • 02_timing_summary.rpt — Post-route timing report
    • 04_utilization.rpt — Post-route utilization report

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t
    Downloads
  • v1.0.0-ft2232h 765aa279ac
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    Stable

    mirror released this 2026-04-07 20:37:05 +00:00 | 91 commits to main since this release

    📅 Originally published on GitHub: Tue, 07 Apr 2026 20:37:36 GMT
    🏷️ Git tag created: Tue, 07 Apr 2026 20:37:05 GMT

    AERIS-10 50T Production Bitstream — FT2232H USB 2.0

    Vivado Build 15 bitstream for the XC7A50T-FTG256 production board with FT2232HQ USB 2.0 (8-bit, 245 Synchronous FIFO) replacing the FT601 USB 3.0 (32-bit) interface.

    Timing

    Metric Value
    WNS +0.088 ns
    WHS +0.059 ns
    WPWS +0.361 ns
    Failing Endpoints 0
    All constraints met Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util%
    LUTs 10,060 32,600 30.9%
    Flip-Flops 12,670 65,200 19.4%
    BRAM 17.5 75 23.3%
    DSP48E1 112 120 93.3%
    IOB 79 170 46.5%

    What Changed (from FT601 baseline)

    • RTL: Parametric USB_MODE in radar_system_top.v — generate block selects FT601 (MODE=0, 200T) or FT2232H (MODE=1, 50T)
    • New module: usb_data_interface_ft2232h.v — 8-bit FIFO interface for Channel A
    • Wrapper: radar_system_top_50t.v instantiates top with .USB_MODE(1)
    • DDC fix: Retiming in DDC chain for 400 MHz timing closure
    • Constraints: xc7a50t_ftg256.xdc updated with FT2232H pin map (Bank 35, 3.3V)
    • Python host: FT601 support removed, FT2232HConnection is the only data interface
    • CI: GitHub Actions running 101 tests (58 Python + 20 MCU C + 23 FPGA iverilog)

    Assets

    • radar_system_top_50t.bit — Production bitstream (program via Vivado/xsdb)
    • 02_timing_summary.rpt — Post-route timing report
    • 04_utilization.rpt — Post-route utilization report

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t
    Downloads