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  • v2.0.1-reset-fanout d0b3a4c969
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    Stable

    mirror released this 2026-04-18 14:49:52 +00:00 | 13 commits to main since this release

    📅 Originally published on GitHub: Sun, 19 Apr 2026 10:37:48 GMT
    🏷️ Git tag created: Sat, 18 Apr 2026 14:49:52 GMT

    AERIS-10 400 MHz Reset Fan-Out Fix + ADAR1000 Channel Indexing

    Hotfix rebuild of the xc7a50t-ftg256-2 production bitstream resolving a 400 MHz clk_dco setup violation (WNS = −0.626 ns) introduced by the reset topology change in v2.0.0-fft2048. Also carries a 1-based channel indexing correction in the ADAR1000 MCU driver (issue #90) that silently wrote the wrong SPI register for channel 1.

    Timing (2026-04-18, commit d0b3a4c)

    Clock Period WNS Failing Endpoints Previous (v2.0.0)
    clk_mmcm_out0 (400 MHz) 2.5 ns +0.020 ns 0 +0.068 ns
    clk_100m (100 MHz) 10.0 ns +0.156 ns 0 +0.156 ns
    clk_120m_dac (120 MHz) 8.333 ns +0.627 ns 0 +0.627 ns
    ft_clkout (60 MHz) 16.667 ns +9.887 ns 0 +9.887 ns
    adc_dco_p (400 MHz) 2.5 ns +0.020 ns 0 +0.920 ns
    Hold (WHS) — +0.035 ns 0 +0.046 ns
    Pulse width (WPWS) — +0.361 ns 0 +0.361 ns
    All constraints met Yes Yes

    Utilization (xc7a50tftg256-2)

    Resource Used Available Util% Previous (v2.0.0)
    LUTs 21,735 32,600 66.67% 21,735 (66.67%)
    Flip-Flops ~14,610 65,200 ~22.41% 14,579 (22.36%)
    BRAM 55.5 75 74.00% 55.5 (74.00%)
    DSP48E1 112 120 93.33% 112 (93.33%)
    F7 Muxes 7,849 16,300 48.15% 7,849 (48.15%)
    F8 Muxes 3,336 8,150 40.93% 3,336 (40.93%)

    FF count increases by ~30 due to reset register replication; dedicated utilization report not generated for this hotfix build.

    What Changed (from v2.0.0-fft2048)

    400 MHz Reset Fan-Out Fix

    • nco_400m_enhanced.v, cic_decimator_4x_enhanced.v, ddc_400m.v: Registered active-high reset reset_h with (* max_fanout=50 *). Prior single-LUT1 inverter drove 700+ loads causing setup violation on the DSP48E1 RSTP path. Vivado now replicates into regional copies (≤50 loads each), meeting setup with +0.020 ns margin.
    • radar_system_top.v: Default USB_MODE changed from 0 (FT601) to 1 (FT2232H). FT601 path remains selectable via explicit parameter override for the 200T premium board.

    MCU — ADAR1000 Channel Indexing (issue #90)

    • ADAR1000_Manager.cpp: Corrected 1-based channel indexing in all phase/gain setters. Prior off-by-one silently addressed the wrong physical SPI register when the caller passed channel 1.
    • test_cross_layer_contract.py: 416-line cross-layer contract test added covering register stride, round-trip correctness for all four setters (adarSetRxPhase, adarSetTxPhase, adarSetRxVgaGain, adarSetTxVgaGain), and caller-site 1-based convention enforcement. Prevents future indexing drift.

    Test Suite

    Layer Tests Status
    Python (GUI) 171 pass, 3 skip Pass
    MCU (C/C++) 88 Pass
    FPGA (iverilog) 27 Pass
    Cross-layer 54 Pass
    Total 340 pass, 3 skip All pass

    Assets

    • xc7a50t-ftg256-prod-2026-04-18.bit — Production bitstream (2,140 KB, program via Vivado/xsdb)
    • xc7a50t-ftg256-prod-timing-2026-04-18.rpt — Post-route timing report
    • xc7a50t-ftg256-prod-2026-04-18.md — Build report and programming instructions

    Build Environment

    • Vivado 2025.2 (lin64)
    • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
    • Top module: radar_system_top_50t (USB_MODE=1, FT2232H)
    • Synth: 152s, Impl: 416s, Bit: ~38s
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