Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Sat Apr 18 18:01:59 2026 | Host : jason-pc running 64-bit Ubuntu 25.10 | Command : report_timing_summary -file /home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA/build_50t/reports_50t/02_timing_summary.rpt | Design : radar_system_top_50t | Device : 7a50t-ftg256 | Speed File : -2 PRODUCTION 1.23 2018-06-13 | Design State : Physopt postRoute ---------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (15) 6. checking no_output_delay (28) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (15) ------------------------------- There are 11 input ports with no input delay specified. (HIGH) There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (28) -------------------------------- There are 28 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.020 0.000 0 37155 0.035 0.000 0 37131 0.361 0.000 0 13052 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- adc_dco_p {0.000 1.250} 2.500 400.000 clk_mmcm_fb_out {0.000 1.250} 2.500 400.000 clk_mmcm_out0 {0.000 1.250} 2.500 400.000 clk_100m {0.000 5.000} 10.000 100.000 clk_120m_dac {0.000 4.167} 8.333 120.005 ft_clkout {0.000 8.334} 16.667 59.999 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- adc_dco_p 0.920 0.000 0 8 0.361 0.000 0 10 clk_mmcm_fb_out 0.908 0.000 0 3 clk_mmcm_out0 0.162 0.000 0 3508 0.091 0.000 0 3508 0.684 0.000 0 782 clk_100m 0.020 0.000 0 31211 0.035 0.000 0 31211 3.870 0.000 0 11876 clk_120m_dac 1.901 0.000 0 102 0.121 0.000 0 102 3.666 0.000 0 70 ft_clkout 11.065 0.000 0 370 0.121 0.000 0 370 7.833 0.000 0 311 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- adc_dco_p clk_mmcm_out0 0.436 0.000 0 16 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_100m clk_100m 1.666 0.000 0 1578 1.675 0.000 0 1578 **async_default** clk_120m_dac clk_120m_dac 5.187 0.000 0 45 0.845 0.000 0 45 **async_default** clk_mmcm_out0 clk_mmcm_out0 0.647 0.000 0 10 0.519 0.000 0 10 **async_default** ft_clkout ft_clkout 8.934 0.000 0 307 0.934 0.000 0 307 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: adc_dco_p Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: adc_d_p[4] (input port clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: adc_dco_p Path Type: Setup (Max at Fast Process Corner) Requirement: 1.250ns (adc_dco_p rise@2.500ns - adc_dco_p fall@1.250ns) Data Path Delay: 0.450ns (logic 0.450ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUFDS=1) Input Delay: 1.000ns Clock Path Skew: 1.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.167ns = ( 3.667 - 2.500 ) Source Clock Delay (SCD): 0.000ns = ( 1.250 - 1.250 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.043ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.050ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock adc_dco_p fall edge) 1.250 1.250 f input delay 1.000 2.250 R10 0.000 2.250 r adc_d_p[4] (IN) net (fo=0) 0.000 2.250 u_core/rx_inst/adc/adc_d_p[4] R10 IBUFDS (Prop_ibufds_I_O) 0.450 2.700 r u_core/rx_inst/adc/data_buffers[4].ibufds_data/O net (fo=1, routed) 0.000 2.700 u_core/rx_inst/adc/adc_data_4 ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D ------------------------------------------------------------------- ------------------- (clock adc_dco_p rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 2.913 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.179 3.092 u_core/rx_inst/adc/adc_dco BUFIO_X0Y2 BUFIO (Prop_bufio_I_O) 0.484 3.576 r u_core/rx_inst/adc/bufio_dco/O net (fo=8, routed) 0.091 3.667 u_core/rx_inst/adc/adc_dco_bufio ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C clock pessimism 0.000 3.667 clock uncertainty -0.043 3.624 ILOGIC_X0Y16 IDDR (Setup_iddr_C_D) -0.003 3.621 u_core/rx_inst/adc/iddr_gen[4].iddr_inst ------------------------------------------------------------------- required time 3.621 arrival time -2.700 ------------------------------------------------------------------- slack 0.920 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: adc_dco_p Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { adc_dco_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDDR/C n/a 1.474 2.500 1.026 ILOGIC_X0Y34 u_core/rx_inst/adc/iddr_gen[0].iddr_inst/C Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_fb_out To Clock: clk_mmcm_fb_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.908ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_fb_out Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 2.500 0.908 BUFGCTRL_X0Y2 u_core/rx_inst/adc/mmcm_inst/bufg_feedback/I Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.162ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.091ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.684ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.162ns (required time - arrival time) Source: u_core/rx_inst/ddc/cic_i_inst/reset_h_reg_rep__21/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/integrator_1_dsp/RSTP (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 2.027ns (logic 0.379ns (18.694%) route 1.648ns (81.306%)) Logic Levels: 0 Clock Path Skew: 0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.077ns = ( 4.577 - 2.500 ) Source Clock Delay (SCD): 2.110ns Clock Pessimism Removal (CPR): 0.072ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 1.515 2.110 u_core/rx_inst/ddc/cic_i_inst/clk_400m SLICE_X41Y108 FDRE r u_core/rx_inst/ddc/cic_i_inst/reset_h_reg_rep__21/C ------------------------------------------------------------------- ------------------- SLICE_X41Y108 FDRE (Prop_fdre_C_Q) 0.379 2.489 r u_core/rx_inst/ddc/cic_i_inst/reset_h_reg_rep__21/Q net (fo=4, routed) 1.648 4.137 u_core/rx_inst/ddc/cic_q_inst/integrator_2_dsp_0 DSP48_X1Y54 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/integrator_1_dsp/RSTP ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 1.480 4.577 u_core/rx_inst/ddc/cic_q_inst/clk_400m DSP48_X1Y54 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/integrator_1_dsp/CLK clock pessimism 0.072 4.649 clock uncertainty -0.053 4.595 DSP48_X1Y54 DSP48E1 (Setup_dsp48e1_CLK_RSTP) -0.296 4.299 u_core/rx_inst/ddc/cic_q_inst/integrator_1_dsp ------------------------------------------------------------------- required time 4.299 arrival time -4.137 ------------------------------------------------------------------- slack 0.162 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.091ns (arrival time - required time) Source: u_core/rx_inst/ddc/cic_q_inst/data_out_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/CDC_FIR_q/src_data_gray_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.444ns (logic 0.209ns (47.063%) route 0.235ns (52.937%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.261ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.936ns Source Clock Delay (SCD): 0.862ns Clock Pessimism Removal (CPR): -0.187ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 0.558 0.862 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X34Y88 FDRE r u_core/rx_inst/ddc/cic_q_inst/data_out_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X34Y88 FDRE (Prop_fdre_C_Q) 0.164 1.026 r u_core/rx_inst/ddc/cic_q_inst/data_out_reg[4]/Q net (fo=2, routed) 0.235 1.261 u_core/rx_inst/ddc/CDC_FIR_q/cic_q_out[4] SLICE_X37Y84 LUT2 (Prop_lut2_I1_O) 0.045 1.306 r u_core/rx_inst/ddc/CDC_FIR_q/src_data_gray[4]_i_1/O net (fo=1, routed) 0.000 1.306 u_core/rx_inst/ddc/CDC_FIR_q/binary_to_gray0_return[4] SLICE_X37Y84 FDRE r u_core/rx_inst/ddc/CDC_FIR_q/src_data_gray_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 0.823 0.936 u_core/rx_inst/ddc/CDC_FIR_q/clk_400m SLICE_X37Y84 FDRE r u_core/rx_inst/ddc/CDC_FIR_q/src_data_gray_reg[4]/C clock pessimism 0.187 1.123 SLICE_X37Y84 FDRE (Hold_fdre_C_D) 0.092 1.215 u_core/rx_inst/ddc/CDC_FIR_q/src_data_gray_reg[4] ------------------------------------------------------------------- required time -1.215 arrival time 1.306 ------------------------------------------------------------------- slack 0.091 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_out0 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 1.816 2.500 0.684 DSP48_X1Y18 u_core/rx_inst/ddc/dsp_mixer_i/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 Low Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X43Y48 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X43Y48 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.020ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.035ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.020ns (required time - arrival time) Source: u_core/rx_inst/ddc_if/adc_q_reg[0]/C (rising edge-triggered cell FDSE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/gain_ctrl/holdoff_counter_reg[3]/D (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.854ns (logic 3.710ns (37.650%) route 6.144ns (62.350%)) Logic Levels: 16 (CARRY4=7 LUT1=1 LUT2=1 LUT3=1 LUT4=1 LUT5=1 LUT6=4) Clock Path Skew: -0.033ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.280ns = ( 14.280 - 10.000 ) Source Clock Delay (SCD): 4.537ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11891, routed) 1.338 4.537 u_core/rx_inst/ddc_if/clk_100m_buf SLICE_X14Y73 FDSE r u_core/rx_inst/ddc_if/adc_q_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X14Y73 FDSE (Prop_fdse_C_Q) 0.433 4.970 f u_core/rx_inst/ddc_if/adc_q_reg[0]/Q net (fo=10, routed) 0.440 5.410 u_core/rx_inst/ddc_if/adc_q_reg[15]_0[0] SLICE_X15Y75 LUT1 (Prop_lut1_I0_O) 0.105 5.515 r u_core/rx_inst/ddc_if/frame_peak[4]_i_10/O net (fo=1, routed) 0.264 5.779 u_core/rx_inst/ddc_if/gain_ctrl/abs_q1[0] SLICE_X14Y77 CARRY4 (Prop_carry4_CYINIT_CO[3]) 0.494 6.273 r u_core/rx_inst/ddc_if/frame_peak_reg[4]_i_4/CO[3] net (fo=1, routed) 0.000 6.273 u_core/rx_inst/ddc_if/frame_peak_reg[4]_i_4_n_0 SLICE_X14Y78 CARRY4 (Prop_carry4_CI_CO[3]) 0.100 6.373 r u_core/rx_inst/ddc_if/frame_peak_reg[6]_i_14/CO[3] net (fo=1, routed) 0.000 6.373 u_core/rx_inst/ddc_if/frame_peak_reg[6]_i_14_n_0 SLICE_X14Y79 CARRY4 (Prop_carry4_CI_O[0]) 0.178 6.551 f u_core/rx_inst/ddc_if/peak_magnitude_reg[5]_i_4/O[0] net (fo=2, routed) 0.494 7.045 u_core/rx_inst/ddc_if/gain_ctrl/abs_q0[9] SLICE_X14Y81 LUT3 (Prop_lut3_I0_O) 0.238 7.283 f u_core/rx_inst/ddc_if/frame_peak[9]_i_3/O net (fo=2, routed) 0.579 7.863 u_core/rx_inst/ddc_if/gain_ctrl/abs_q__0[9] SLICE_X13Y80 LUT6 (Prop_lut6_I4_O) 0.105 7.968 r u_core/rx_inst/ddc_if/frame_peak[6]_i_9/O net (fo=1, routed) 0.372 8.339 u_core/rx_inst/ddc_if/frame_peak[6]_i_9_n_0 SLICE_X12Y79 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.457 8.796 r u_core/rx_inst/ddc_if/frame_peak_reg[6]_i_2/CO[3] net (fo=29, routed) 0.765 9.562 u_core/rx_inst/ddc_if/gain_ctrl/max_iq1 SLICE_X10Y77 LUT5 (Prop_lut5_I4_O) 0.105 9.667 r u_core/rx_inst/ddc_if/frame_peak[14]_i_30/O net (fo=2, routed) 0.372 10.038 u_core/rx_inst/ddc_if/gain_ctrl/max_iq__0[1] SLICE_X10Y77 LUT6 (Prop_lut6_I5_O) 0.105 10.143 r u_core/rx_inst/ddc_if/frame_peak[14]_i_18/O net (fo=1, routed) 0.264 10.407 u_core/rx_inst/ddc_if/frame_peak[14]_i_18_n_0 SLICE_X11Y79 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.436 10.843 r u_core/rx_inst/ddc_if/frame_peak_reg[14]_i_5/CO[3] net (fo=1, routed) 0.000 10.843 u_core/rx_inst/ddc_if/frame_peak_reg[14]_i_5_n_0 SLICE_X11Y80 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 10.941 r u_core/rx_inst/ddc_if/frame_peak_reg[14]_i_3/CO[3] net (fo=10, routed) 0.549 11.490 u_core/rx_inst/ddc_if/CO[0] SLICE_X11Y81 LUT2 (Prop_lut2_I1_O) 0.105 11.595 r u_core/rx_inst/ddc_if/holdoff_counter[2]_i_13/O net (fo=8, routed) 0.518 12.113 u_core/rx_inst/ddc_if/gain_ctrl/peak_magnitude2 SLICE_X12Y83 LUT6 (Prop_lut6_I2_O) 0.105 12.218 r u_core/rx_inst/ddc_if/holdoff_counter[2]_i_8/O net (fo=1, routed) 0.144 12.362 u_core/rx_inst/ddc_if/holdoff_counter[2]_i_8_n_0 SLICE_X13Y83 CARRY4 (Prop_carry4_DI[0]_CO[3]) 0.436 12.798 r u_core/rx_inst/ddc_if/holdoff_counter_reg[2]_i_4/CO[3] net (fo=6, routed) 0.632 13.430 u_core/rx_inst/gain_ctrl/holdoff_counter_reg[1]_0[0] SLICE_X14Y83 LUT6 (Prop_lut6_I4_O) 0.105 13.535 r u_core/rx_inst/gain_ctrl/holdoff_counter[3]_i_4/O net (fo=1, routed) 0.374 13.910 u_core/rx_inst/gain_ctrl/holdoff_counter[3]_i_4_n_0 SLICE_X15Y83 LUT4 (Prop_lut4_I3_O) 0.105 14.015 r u_core/rx_inst/gain_ctrl/holdoff_counter[3]_i_2/O net (fo=1, routed) 0.376 14.391 u_core/rx_inst/gain_ctrl/holdoff_counter[3]_i_2_n_0 SLICE_X15Y83 FDCE r u_core/rx_inst/gain_ctrl/holdoff_counter_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11891, routed) 1.240 14.280 u_core/rx_inst/gain_ctrl/clk_100m_buf SLICE_X15Y83 FDCE r u_core/rx_inst/gain_ctrl/holdoff_counter_reg[3]/C clock pessimism 0.224 14.504 clock uncertainty -0.061 14.443 SLICE_X15Y83 FDCE (Setup_fdce_C_D) -0.032 14.411 u_core/rx_inst/gain_ctrl/holdoff_counter_reg[3] ------------------------------------------------------------------- required time 14.411 arrival time -14.391 ------------------------------------------------------------------- slack 0.020 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.035ns (arrival time - required time) Source: u_core/rx_inst/ddc/fir_q_inst/add_l2_reg[2][3]/C (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/ddc/fir_q_inst/add_l3_reg[1][12]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 0.520ns (logic 0.428ns (82.338%) route 0.092ns (17.662%)) Logic Levels: 5 (CARRY4=4 LUT2=1) Clock Path Skew: 0.350ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.085ns Source Clock Delay (SCD): 1.484ns Clock Pessimism Removal (CPR): 0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11891, routed) 0.563 1.484 u_core/rx_inst/ddc/fir_q_inst/clk_100m_buf SLICE_X51Y97 FDRE r u_core/rx_inst/ddc/fir_q_inst/add_l2_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X51Y97 FDRE (Prop_fdre_C_Q) 0.141 1.625 r u_core/rx_inst/ddc/fir_q_inst/add_l2_reg[2][3]/Q net (fo=2, routed) 0.091 1.717 u_core/rx_inst/ddc/fir_q_inst/add_l2_reg[2][31]_0[3] SLICE_X50Y97 LUT2 (Prop_lut2_I0_O) 0.045 1.762 r u_core/rx_inst/ddc/fir_q_inst/add_l3[1][3]_i_2/O net (fo=1, routed) 0.000 1.762 u_core/rx_inst_n_1651 SLICE_X50Y97 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.109 1.871 r u_core/ddc/fir_q_inst/add_l3_reg[1][3]_i_1/CO[3] net (fo=1, routed) 0.000 1.871 u_core/ddc/fir_q_inst/add_l3_reg[1][3]_i_1_n_0 SLICE_X50Y98 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 1.911 r u_core/ddc/fir_q_inst/add_l3_reg[1][7]_i_1/CO[3] net (fo=1, routed) 0.000 1.911 u_core/ddc/fir_q_inst/add_l3_reg[1][7]_i_1_n_0 SLICE_X50Y99 CARRY4 (Prop_carry4_CI_CO[3]) 0.040 1.951 r u_core/ddc/fir_q_inst/add_l3_reg[1][11]_i_1/CO[3] net (fo=1, routed) 0.001 1.951 u_core/ddc/fir_q_inst/add_l3_reg[1][11]_i_1_n_0 SLICE_X50Y100 CARRY4 (Prop_carry4_CI_O[0]) 0.053 2.004 r u_core/ddc/fir_q_inst/add_l3_reg[1][15]_i_1/O[0] net (fo=1, routed) 0.000 2.004 u_core/rx_inst/ddc/fir_q_inst/add_l3_reg[1][31]_0[12] SLICE_X50Y100 FDRE r u_core/rx_inst/ddc/fir_q_inst/add_l3_reg[1][12]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11891, routed) 0.918 2.085 u_core/rx_inst/ddc/fir_q_inst/clk_100m_buf SLICE_X50Y100 FDRE r u_core/rx_inst/ddc/fir_q_inst/add_l3_reg[1][12]/C clock pessimism -0.251 1.835 SLICE_X50Y100 FDRE (Hold_fdre_C_D) 0.134 1.969 u_core/rx_inst/ddc/fir_q_inst/add_l3_reg[1][12] ------------------------------------------------------------------- required time -1.969 arrival time 2.004 ------------------------------------------------------------------- slack 0.035 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100m Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100m } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.272 10.000 6.728 DSP48_X0Y0 u_core/rx_inst/ddc/fir_i_inst/mult_reg_reg[0]/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X6Y115 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X6Y115 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 1.901ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.901ns (required time - arrival time) Source: u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C (rising edge-triggered cell FDPE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 (falling edge-triggered cell ODDR clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (clk_120m_dac fall@4.167ns - clk_120m_dac rise@0.000ns) Data Path Delay: 1.320ns (logic 0.348ns (26.355%) route 0.972ns (73.645%)) Logic Levels: 0 Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.339ns = ( 8.506 - 4.167 ) Source Clock Delay (SCD): 4.603ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.404 4.603 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf SLICE_X0Y75 FDPE r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y75 FDPE (Prop_fdpe_C_Q) 0.348 4.951 r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/Q net (fo=2, routed) 0.972 5.924 u_core/tx_inst/dac_interface_inst/dac_data_reg[7] OLOGIC_X0Y96 ODDR r u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 ------------------------------------------------------------------- ------------------- (clock clk_120m_dac fall edge) 4.167 4.167 f D13 0.000 4.167 f clk_120m_dac (IN) net (fo=0) 0.000 4.167 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 5.526 f clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 7.130 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 7.207 f u_core/bufg_120m/O net (fo=69, routed) 1.299 8.506 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf OLOGIC_X0Y96 ODDR f u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/C clock pessimism 0.224 8.730 clock uncertainty -0.061 8.668 OLOGIC_X0Y96 ODDR (Setup_oddr_C_D2) -0.844 7.824 u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data ------------------------------------------------------------------- required time 7.824 arrival time -5.924 ------------------------------------------------------------------- slack 1.901 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.014ns Source Clock Delay (SCD): 1.501ns Clock Pessimism Removal (CPR): 0.513ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.579 1.501 u_core/tx_inst/cdc_mixers_en_120m/clk_120m_dac_buf SLICE_X1Y76 FDRE r u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y76 FDRE (Prop_fdre_C_Q) 0.141 1.642 r u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[0]/Q net (fo=1, routed) 0.055 1.697 u_core/tx_inst/cdc_mixers_en_120m/sync_chain[0] SLICE_X1Y76 FDRE r u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.846 2.014 u_core/tx_inst/cdc_mixers_en_120m/clk_120m_dac_buf SLICE_X1Y76 FDRE r u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[1]/C clock pessimism -0.513 1.501 SLICE_X1Y76 FDRE (Hold_fdre_C_D) 0.075 1.576 u_core/tx_inst/cdc_mixers_en_120m/sync_chain_reg[1] ------------------------------------------------------------------- required time -1.576 arrival time 1.697 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_120m_dac Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { clk_120m_dac } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.170 8.333 6.163 RAMB36_X0Y15 u_core/tx_inst/plfm_chirp_inst/long_chirp_rd_data_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X2Y78 u_core/chirp_frame_toggle_120m_reg/C High Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X2Y78 u_core/chirp_frame_toggle_120m_reg/C --------------------------------------------------------------------------------------------------- From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 11.065ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 11.065ns (required time - arrival time) Source: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/ft_data_out_reg[7]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 5.507ns (logic 0.825ns (14.980%) route 4.682ns (85.020%)) Logic Levels: 3 (LUT5=1 LUT6=1 MUXF7=1) Clock Path Skew: -0.048ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.074ns = ( 21.741 - 16.667 ) Source Clock Delay (SCD): 5.611ns Clock Pessimism Removal (CPR): 0.489ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=310, routed) 1.518 5.611 u_core/gen_ft2232h.usb_inst/CLK SLICE_X54Y109 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X54Y109 FDCE (Prop_fdce_C_Q) 0.433 6.044 r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/Q net (fo=82, routed) 3.258 9.302 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg_n_0_[0] SLICE_X49Y95 LUT5 (Prop_lut5_I4_O) 0.105 9.407 r u_core/gen_ft2232h.usb_inst/ft_data_out[7]_i_8/O net (fo=1, routed) 1.425 10.831 u_core/gen_ft2232h.usb_inst/ft_data_out[7]_i_8_n_0 SLICE_X41Y112 LUT6 (Prop_lut6_I0_O) 0.105 10.936 r u_core/gen_ft2232h.usb_inst/ft_data_out[7]_i_4/O net (fo=1, routed) 0.000 10.936 u_core/gen_ft2232h.usb_inst/ft_data_out[7]_i_4_n_0 SLICE_X41Y112 MUXF7 (Prop_muxf7_I1_O) 0.182 11.118 r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[7]_i_2/O net (fo=1, routed) 0.000 11.118 u_core/gen_ft2232h.usb_inst/ft_data_out0_in[7] SLICE_X41Y112 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[7]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=310, routed) 1.396 21.741 u_core/gen_ft2232h.usb_inst/CLK SLICE_X41Y112 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[7]/C clock pessimism 0.489 22.230 clock uncertainty -0.106 22.124 SLICE_X41Y112 FDCE (Setup_fdce_C_D) 0.060 22.184 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[7] ------------------------------------------------------------------- required time 22.184 arrival time -11.118 ------------------------------------------------------------------- slack 11.065 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[1]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.951ns Source Clock Delay (SCD): 2.302ns Clock Pessimism Removal (CPR): 0.649ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=310, routed) 0.644 2.302 u_core/gen_ft2232h.usb_inst/CLK SLICE_X53Y109 FDCE r u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y109 FDCE (Prop_fdce_C_Q) 0.141 2.443 r u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[0]/Q net (fo=1, routed) 0.055 2.498 u_core/gen_ft2232h.usb_inst/status_toggle_sync[0] SLICE_X53Y109 FDCE r u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=310, routed) 0.918 2.951 u_core/gen_ft2232h.usb_inst/CLK SLICE_X53Y109 FDCE r u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[1]/C clock pessimism -0.649 2.302 SLICE_X53Y109 FDCE (Hold_fdce_C_D) 0.075 2.377 u_core/gen_ft2232h.usb_inst/status_toggle_sync_reg[1] ------------------------------------------------------------------- required time -2.377 arrival time 2.498 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ft_clkout Waveform(ns): { 0.000 8.333 } Period(ns): 16.667 Sources: { ft_clkout } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 16.667 15.075 BUFGCTRL_X0Y1 u_core/bufg_ft601/I Low Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X39Y112 u_core/cmd_valid_toggle_ft601_reg/C High Pulse Width Slow FDCE/C n/a 0.500 8.333 7.833 SLICE_X39Y112 u_core/cmd_valid_toggle_ft601_reg/C --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.436ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.436ns (required time - arrival time) Source: u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_rise_bufg_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (MaxDelay Path 2.500ns) Data Path Delay: 1.956ns (logic 0.448ns (22.901%) route 1.508ns (77.099%)) Logic Levels: 0 Timing Exception: MaxDelay Path 2.500ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- ILOGIC_X0Y2 0.000 0.000 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C ILOGIC_X0Y2 IDDR (Prop_iddr_C_Q1) 0.448 0.448 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/Q1 net (fo=1, routed) 1.508 1.956 u_core/rx_inst/adc/adc_data_rise[7] SLICE_X28Y16 FDRE r u_core/rx_inst/adc/adc_data_rise_bufg_reg[7]/D ------------------------------------------------------------------- ------------------- max delay 2.500 2.500 SLICE_X28Y16 FDRE (Setup_fdre_C_D) -0.108 2.392 u_core/rx_inst/adc/adc_data_rise_bufg_reg[7] ------------------------------------------------------------------- required time 2.392 arrival time -1.956 ------------------------------------------------------------------- slack 0.436 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 1.666ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.675ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.666ns (required time - arrival time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/cfar_inst/leading_count_reg[2]/CLR (recovery check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 7.979ns (logic 0.590ns (7.394%) route 7.389ns (92.606%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.001ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.440ns = ( 14.440 - 10.000 ) Source Clock Delay (SCD): 4.606ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11891, routed) 1.407 4.606 u_core/clk_100m_buf SLICE_X0Y77 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y77 FDCE (Prop_fdce_C_Q) 0.348 4.954 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 1.266 6.220 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X0Y45 LUT1 (Prop_lut1_I0_O) 0.242 6.462 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4579, routed) 6.123 12.585 u_core/cfar_inst/RST0 SLICE_X52Y143 FDCE f u_core/cfar_inst/leading_count_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11891, routed) 1.400 14.440 u_core/cfar_inst/clk_100m_buf SLICE_X52Y143 FDCE r u_core/cfar_inst/leading_count_reg[2]/C clock pessimism 0.165 14.605 clock uncertainty -0.061 14.543 SLICE_X52Y143 FDCE (Recov_fdce_C_CLR) -0.292 14.251 u_core/cfar_inst/leading_count_reg[2] ------------------------------------------------------------------- required time 14.251 arrival time -12.585 ------------------------------------------------------------------- slack 1.666 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.675ns (arrival time - required time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/doppler_proc/fft_inst/fft_core/FSM_onehot_state_reg[4]/CLR (removal check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 1.927ns (logic 0.227ns (11.779%) route 1.700ns (88.221%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.344ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.097ns Source Clock Delay (SCD): 1.502ns Clock Pessimism Removal (CPR): 0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11891, routed) 0.581 1.502 u_core/clk_100m_buf SLICE_X0Y77 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y77 FDCE (Prop_fdce_C_Q) 0.128 1.630 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 0.653 2.284 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X0Y45 LUT1 (Prop_lut1_I0_O) 0.099 2.383 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4579, routed) 1.047 3.430 u_core/rx_inst/doppler_proc/fft_inst/fft_core/bf_prod_re1__0_0 SLICE_X7Y125 FDCE f u_core/rx_inst/doppler_proc/fft_inst/fft_core/FSM_onehot_state_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11891, routed) 0.930 2.097 u_core/rx_inst/doppler_proc/fft_inst/fft_core/clk_100m_buf SLICE_X7Y125 FDCE r u_core/rx_inst/doppler_proc/fft_inst/fft_core/FSM_onehot_state_reg[4]/C clock pessimism -0.251 1.847 SLICE_X7Y125 FDCE (Remov_fdce_C_CLR) -0.092 1.755 u_core/rx_inst/doppler_proc/fft_inst/fft_core/FSM_onehot_state_reg[4] ------------------------------------------------------------------- required time -1.755 arrival time 3.430 ------------------------------------------------------------------- slack 1.675 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 5.187ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.845ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.187ns (required time - arrival time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/CLR (recovery check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 2.701ns (logic 0.590ns (21.845%) route 2.111ns (78.155%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.339ns = ( 12.672 - 8.333 ) Source Clock Delay (SCD): 4.615ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.416 4.615 u_core/clk_120m_dac_buf SLICE_X0Y85 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y85 FDCE (Prop_fdce_C_Q) 0.348 4.963 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.685 5.648 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X0Y85 LUT1 (Prop_lut1_I0_O) 0.242 5.890 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 1.426 7.316 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X7Y74 FDCE f u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.298 12.672 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X7Y74 FDCE r u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/C clock pessimism 0.224 12.895 clock uncertainty -0.061 12.834 SLICE_X7Y74 FDCE (Recov_fdce_C_CLR) -0.331 12.503 u_core/tx_inst/plfm_chirp_inst/current_state_reg[2] ------------------------------------------------------------------- required time 12.503 arrival time -7.316 ------------------------------------------------------------------- slack 5.187 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.845ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/chirp_frame_toggle_120m_reg/CLR (removal check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.786ns (logic 0.227ns (28.867%) route 0.559ns (71.133%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.017ns Source Clock Delay (SCD): 1.509ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.587 1.509 u_core/clk_120m_dac_buf SLICE_X0Y85 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y85 FDCE (Prop_fdce_C_Q) 0.128 1.637 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.279 1.916 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X0Y85 LUT1 (Prop_lut1_I0_O) 0.099 2.015 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 0.280 2.295 u_core/tx_inst_n_11 SLICE_X2Y78 FDCE f u_core/chirp_frame_toggle_120m_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.850 2.017 u_core/clk_120m_dac_buf SLICE_X2Y78 FDCE r u_core/chirp_frame_toggle_120m_reg/C clock pessimism -0.500 1.517 SLICE_X2Y78 FDCE (Remov_fdce_C_CLR) -0.067 1.450 u_core/chirp_frame_toggle_120m_reg ------------------------------------------------------------------- required time -1.450 arrival time 2.295 ------------------------------------------------------------------- slack 0.845 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.647ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.519ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.647ns (required time - arrival time) Source: u_core/rx_inst/adc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/PRE (recovery check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.462ns (logic 0.484ns (33.103%) route 0.978ns (66.897%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.046ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.853ns = ( 4.353 - 2.500 ) Source Clock Delay (SCD): 1.963ns Clock Pessimism Removal (CPR): 0.064ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 1.368 1.963 u_core/rx_inst/adc/clk_400m SLICE_X43Y42 FDCE r u_core/rx_inst/adc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y42 FDCE (Prop_fdce_C_Q) 0.379 2.342 r u_core/rx_inst/adc/reset_sync_400m_reg[1]/Q net (fo=1, routed) 0.130 2.472 u_core/rx_inst/adc/reset_sync_400m[1] SLICE_X42Y42 LUT1 (Prop_lut1_I0_O) 0.105 2.577 f u_core/rx_inst/adc/dco_phase_i_2/O net (fo=10, routed) 0.848 3.425 u_core/rx_inst/adc/dco_phase_i_2_n_0 SLICE_X49Y32 FDPE f u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/PRE ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 1.256 4.353 u_core/rx_inst/adc/clk_400m SLICE_X49Y32 FDPE r u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/C clock pessimism 0.064 4.417 clock uncertainty -0.053 4.364 SLICE_X49Y32 FDPE (Recov_fdpe_C_PRE) -0.292 4.072 u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv ------------------------------------------------------------------- required time 4.072 arrival time -3.425 ------------------------------------------------------------------- slack 0.647 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.519ns (arrival time - required time) Source: u_core/rx_inst/adc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_400m_reg_reg[2]/CLR (removal check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.443ns (logic 0.186ns (41.971%) route 0.257ns (58.029%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.944ns Source Clock Delay (SCD): 0.866ns Clock Pessimism Removal (CPR): 0.062ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 0.562 0.866 u_core/rx_inst/adc/clk_400m SLICE_X43Y42 FDCE r u_core/rx_inst/adc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X43Y42 FDCE (Prop_fdce_C_Q) 0.141 1.007 r u_core/rx_inst/adc/reset_sync_400m_reg[1]/Q net (fo=1, routed) 0.051 1.059 u_core/rx_inst/adc/reset_sync_400m[1] SLICE_X42Y42 LUT1 (Prop_lut1_I0_O) 0.045 1.104 f u_core/rx_inst/adc/dco_phase_i_2/O net (fo=10, routed) 0.206 1.309 u_core/rx_inst/adc/dco_phase_i_2_n_0 SLICE_X40Y42 FDCE f u_core/rx_inst/adc/adc_data_400m_reg_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=780, routed) 0.832 0.944 u_core/rx_inst/adc/clk_400m SLICE_X40Y42 FDCE r u_core/rx_inst/adc/adc_data_400m_reg_reg[2]/C clock pessimism -0.062 0.882 SLICE_X40Y42 FDCE (Remov_fdce_C_CLR) -0.092 0.790 u_core/rx_inst/adc/adc_data_400m_reg_reg[2] ------------------------------------------------------------------- required time -0.790 arrival time 1.309 ------------------------------------------------------------------- slack 0.519 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 8.934ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.934ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 8.934ns (required time - arrival time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[13]/CLR (recovery check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 7.343ns (logic 0.587ns (7.994%) route 6.756ns (92.006%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.069ns = ( 21.736 - 16.667 ) Source Clock Delay (SCD): 5.516ns Clock Pessimism Removal (CPR): 0.421ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=310, routed) 1.423 5.516 u_core/ft601_clk_buf SLICE_X1Y89 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y89 FDCE (Prop_fdce_C_Q) 0.348 5.864 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.530 6.394 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X2Y90 LUT1 (Prop_lut1_I0_O) 0.239 6.633 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 6.227 12.859 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X30Y119 FDCE f u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=310, routed) 1.391 21.736 u_core/gen_ft2232h.usb_inst/CLK SLICE_X30Y119 FDCE r u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[13]/C clock pessimism 0.421 22.158 clock uncertainty -0.106 22.051 SLICE_X30Y119 FDCE (Recov_fdce_C_CLR) -0.258 21.793 u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[13] ------------------------------------------------------------------- required time 21.793 arrival time -12.859 ------------------------------------------------------------------- slack 8.934 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.934ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_words_reg[4][18]/CLR (removal check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 1.101ns (logic 0.226ns (20.524%) route 0.875ns (79.476%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.234ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.863ns Source Clock Delay (SCD): 2.249ns Clock Pessimism Removal (CPR): 0.380ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=310, routed) 0.591 2.249 u_core/ft601_clk_buf SLICE_X1Y89 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y89 FDCE (Prop_fdce_C_Q) 0.128 2.377 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.210 2.587 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X2Y90 LUT1 (Prop_lut1_I0_O) 0.098 2.685 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 0.665 3.350 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X38Y95 FDCE f u_core/gen_ft2232h.usb_inst/status_words_reg[4][18]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=310, routed) 0.829 2.863 u_core/gen_ft2232h.usb_inst/CLK SLICE_X38Y95 FDCE r u_core/gen_ft2232h.usb_inst/status_words_reg[4][18]/C clock pessimism -0.380 2.483 SLICE_X38Y95 FDCE (Remov_fdce_C_CLR) -0.067 2.416 u_core/gen_ft2232h.usb_inst/status_words_reg[4][18] ------------------------------------------------------------------- required time -2.416 arrival time 3.350 ------------------------------------------------------------------- slack 0.934