Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Tue Apr 7 19:20:09 2026 | Host : jason-pc running 64-bit Ubuntu 25.10 | Command : report_timing_summary -file /home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA/build_50t/reports_50t/02_timing_summary.rpt | Design : radar_system_top_50t | Device : 7a50t-ftg256 | Speed File : -2 PRODUCTION 1.23 2018-06-13 | Design State : Physopt postRoute ---------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (15) 6. checking no_output_delay (26) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (15) ------------------------------- There are 11 input ports with no input delay specified. (HIGH) There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (26) -------------------------------- There are 26 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.088 0.000 0 36761 0.059 0.000 0 36737 0.361 0.000 0 12925 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- adc_dco_p {0.000 1.250} 2.500 400.000 clk_mmcm_fb_out {0.000 1.250} 2.500 400.000 clk_mmcm_out0 {0.000 1.250} 2.500 400.000 clk_100m {0.000 5.000} 10.000 100.000 clk_120m_dac {0.000 4.167} 8.333 120.005 ft_clkout {0.000 8.334} 16.667 59.999 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- adc_dco_p 0.920 0.000 0 8 0.361 0.000 0 10 clk_mmcm_fb_out 0.908 0.000 0 3 clk_mmcm_out0 0.088 0.000 0 3169 0.072 0.000 0 3169 0.684 0.000 0 748 clk_100m 0.422 0.000 0 31091 0.059 0.000 0 31091 3.870 0.000 0 11805 clk_120m_dac 0.722 0.000 0 102 0.121 0.000 0 102 3.666 0.000 0 70 ft_clkout 11.660 0.000 0 348 0.121 0.000 0 348 7.833 0.000 0 289 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- adc_dco_p clk_mmcm_out0 0.242 0.000 0 16 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_100m clk_100m 1.104 0.000 0 1507 1.686 0.000 0 1507 **async_default** clk_120m_dac clk_120m_dac 3.585 0.000 0 45 1.278 0.000 0 45 **async_default** clk_mmcm_out0 clk_mmcm_out0 0.360 0.000 0 310 0.279 0.000 0 310 **async_default** ft_clkout ft_clkout 13.228 0.000 0 165 0.698 0.000 0 165 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: adc_dco_p Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: adc_d_p[4] (input port clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: adc_dco_p Path Type: Setup (Max at Fast Process Corner) Requirement: 1.250ns (adc_dco_p rise@2.500ns - adc_dco_p fall@1.250ns) Data Path Delay: 0.450ns (logic 0.450ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUFDS=1) Input Delay: 1.000ns Clock Path Skew: 1.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.167ns = ( 3.667 - 2.500 ) Source Clock Delay (SCD): 0.000ns = ( 1.250 - 1.250 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.043ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.050ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock adc_dco_p fall edge) 1.250 1.250 f input delay 1.000 2.250 R10 0.000 2.250 r adc_d_p[4] (IN) net (fo=0) 0.000 2.250 u_core/rx_inst/adc/adc_d_p[4] R10 IBUFDS (Prop_ibufds_I_O) 0.450 2.700 r u_core/rx_inst/adc/data_buffers[4].ibufds_data/O net (fo=1, routed) 0.000 2.700 u_core/rx_inst/adc/adc_data_4 ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D ------------------------------------------------------------------- ------------------- (clock adc_dco_p rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 2.913 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.179 3.092 u_core/rx_inst/adc/adc_dco BUFIO_X0Y2 BUFIO (Prop_bufio_I_O) 0.484 3.576 r u_core/rx_inst/adc/bufio_dco/O net (fo=8, routed) 0.091 3.667 u_core/rx_inst/adc/adc_dco_bufio ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C clock pessimism 0.000 3.667 clock uncertainty -0.043 3.624 ILOGIC_X0Y16 IDDR (Setup_iddr_C_D) -0.003 3.621 u_core/rx_inst/adc/iddr_gen[4].iddr_inst ------------------------------------------------------------------- required time 3.621 arrival time -2.700 ------------------------------------------------------------------- slack 0.920 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: adc_dco_p Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { adc_dco_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDDR/C n/a 1.474 2.500 1.026 ILOGIC_X0Y34 u_core/rx_inst/adc/iddr_gen[0].iddr_inst/C Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_fb_out To Clock: clk_mmcm_fb_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.908ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_fb_out Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 2.500 0.908 BUFGCTRL_X0Y2 u_core/rx_inst/adc/mmcm_inst/bufg_feedback/I Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.088ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.072ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.684ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.088ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/comb_reg[4]/RSTB (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 2.246ns (logic 0.590ns (26.272%) route 1.656ns (73.728%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.344ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.459ns = ( 4.959 - 2.500 ) Source Clock Delay (SCD): 2.112ns Clock Pessimism Removal (CPR): -0.002ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 1.517 2.112 u_core/rx_inst/ddc/bufg_clk400m_0_repN_1_alias SLICE_X41Y104 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y104 FDCE (Prop_fdce_C_Q) 0.348 2.460 f u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=6, routed) 0.281 2.741 u_core/rx_inst/ddc/cic_i_inst/out[0] SLICE_X41Y105 LUT1 (Prop_lut1_I0_O) 0.242 2.983 r u_core/rx_inst/ddc/cic_i_inst/reset_n_400m_inst_replica/O net (fo=301, routed) 1.375 4.358 u_core/rx_inst/ddc/cic_q_inst/p_0_in__0_repN_alias DSP48_X1Y49 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[4]/RSTB ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.112 3.209 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.286 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.126 3.412 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.489 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 1.470 4.959 u_core/rx_inst/ddc/cic_q_inst/clk_400m DSP48_X1Y49 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[4]/CLK clock pessimism -0.002 4.956 clock uncertainty -0.053 4.903 DSP48_X1Y49 DSP48E1 (Setup_dsp48e1_CLK_RSTB) -0.458 4.445 u_core/rx_inst/ddc/cic_q_inst/comb_reg[4] ------------------------------------------------------------------- required time 4.445 arrival time -4.358 ------------------------------------------------------------------- slack 0.088 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.072ns (arrival time - required time) Source: u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[1]/D (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.442ns (logic 0.251ns (56.763%) route 0.191ns (43.237%)) Logic Levels: 2 (CARRY4=1 LUT1=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.080ns Source Clock Delay (SCD): 0.989ns Clock Pessimism Removal (CPR): -0.174ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.030 0.335 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.026 0.361 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.042 0.403 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.429 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 0.561 0.989 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X35Y97 FDPE r u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X35Y97 FDPE (Prop_fdpe_C_Q) 0.141 1.130 f u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[1]/Q net (fo=2, routed) 0.191 1.321 u_core/rx_inst/ddc/nco_core/cos_abs_reg[1] SLICE_X37Y98 LUT1 (Prop_lut1_I0_O) 0.045 1.366 r u_core/rx_inst/ddc/nco_core/cos_neg_reg[3]_i_4/O net (fo=1, routed) 0.000 1.366 u_core/rx_inst_n_2093 SLICE_X37Y98 CARRY4 (Prop_carry4_S[1]_O[1]) 0.065 1.431 r u_core/ddc/nco_core/cos_neg_reg_reg[3]_i_1/O[1] net (fo=1, routed) 0.000 1.431 u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[11]_0[1] SLICE_X37Y98 FDCE r u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.033 0.146 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.175 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.046 0.221 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.250 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 0.830 1.080 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X37Y98 FDCE r u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[1]/C clock pessimism 0.174 1.254 SLICE_X37Y98 FDCE (Hold_fdce_C_D) 0.105 1.359 u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[1] ------------------------------------------------------------------- required time -1.359 arrival time 1.431 ------------------------------------------------------------------- slack 0.072 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_out0 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 1.816 2.500 0.684 DSP48_X0Y38 u_core/rx_inst/ddc/dsp_mixer_i/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 Low Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X11Y65 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X11Y65 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.422ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.059ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.422ns (required time - arrival time) Source: u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__1/CLK (rising edge-triggered cell DSP48E1 clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im_reg[45]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.256ns (logic 5.639ns (60.923%) route 3.617ns (39.077%)) Logic Levels: 4 (CARRY4=2 DSP48E1=1 LUT3=1) Clock Path Skew: -0.320ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.304ns = ( 14.304 - 10.000 ) Source Clock Delay (SCD): 4.782ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11820, routed) 1.584 4.782 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/clk_100m_buf DSP48_X1Y51 DSP48E1 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__1/CLK ------------------------------------------------------------------- ------------------- DSP48_X1Y51 DSP48E1 (Prop_dsp48e1_CLK_PCOUT[47]) 3.541 8.323 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__1/PCOUT[47] net (fo=1, routed) 0.002 8.325 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__1_n_106 DSP48_X1Y52 DSP48E1 (Prop_dsp48e1_PCIN[47]_P[24]) 1.271 9.596 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__2/P[24] net (fo=1, routed) 3.615 13.211 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im1__3[41] SLICE_X53Y39 LUT3 (Prop_lut3_I0_O) 0.105 13.316 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im0_carry__9_i_3/O net (fo=1, routed) 0.000 13.316 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im0_carry__9_i_3_n_0 SLICE_X53Y39 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.457 13.773 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im0_carry__9/CO[3] net (fo=1, routed) 0.000 13.773 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im0_carry__9_n_0 SLICE_X53Y40 CARRY4 (Prop_carry4_CI_O[1]) 0.265 14.038 r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im0_carry__10/O[1] net (fo=1, routed) 0.000 14.038 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im[45] SLICE_X53Y40 FDRE r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im_reg[45]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11820, routed) 1.264 14.304 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/clk_100m_buf SLICE_X53Y40 FDRE r u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im_reg[45]/C clock pessimism 0.159 14.463 clock uncertainty -0.061 14.401 SLICE_X53Y40 FDRE (Setup_fdre_C_D) 0.059 14.460 u_core/rx_inst/mf_dual/m_f_p_c/fft_inst/bf_prod_im_reg[45] ------------------------------------------------------------------- required time 14.460 arrival time -14.038 ------------------------------------------------------------------- slack 0.422 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.059ns (arrival time - required time) Source: u_core/rx_inst/ddc/fir_i_inst/add_l1_reg[4][13]/C (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][13]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 0.456ns (logic 0.252ns (55.209%) route 0.204ns (44.791%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.000ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11820, routed) 0.569 1.490 u_core/rx_inst/ddc/fir_i_inst/clk_100m_buf SLICE_X55Y49 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l1_reg[4][13]/C ------------------------------------------------------------------- ------------------- SLICE_X55Y49 FDRE (Prop_fdre_C_Q) 0.141 1.631 r u_core/rx_inst/ddc/fir_i_inst/add_l1_reg[4][13]/Q net (fo=2, routed) 0.204 1.836 u_core/rx_inst/ddc/fir_i_inst/add_l1_reg[4][31]_0[13] SLICE_X54Y54 LUT2 (Prop_lut2_I0_O) 0.045 1.881 r u_core/rx_inst/ddc/fir_i_inst/add_l2[2][15]_i_4/O net (fo=1, routed) 0.000 1.881 u_core/rx_inst_n_893 SLICE_X54Y54 CARRY4 (Prop_carry4_S[1]_O[1]) 0.066 1.947 r u_core/ddc/fir_i_inst/add_l2_reg[2][15]_i_1/O[1] net (fo=1, routed) 0.000 1.947 u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][31]_2[13] SLICE_X54Y54 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][13]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11820, routed) 0.832 2.000 u_core/rx_inst/ddc/fir_i_inst/clk_100m_buf SLICE_X54Y54 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][13]/C clock pessimism -0.246 1.754 SLICE_X54Y54 FDRE (Hold_fdre_C_D) 0.134 1.888 u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][13] ------------------------------------------------------------------- required time -1.888 arrival time 1.947 ------------------------------------------------------------------- slack 0.059 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100m Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100m } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.272 10.000 6.728 DSP48_X1Y2 u_core/rx_inst/ddc/fir_i_inst/mult_reg_reg[0]/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X8Y99 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X8Y99 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 0.722ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.722ns (required time - arrival time) Source: u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C (rising edge-triggered cell FDPE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 (falling edge-triggered cell ODDR clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (clk_120m_dac fall@4.167ns - clk_120m_dac rise@0.000ns) Data Path Delay: 2.496ns (logic 0.348ns (13.941%) route 2.148ns (86.059%)) Logic Levels: 0 Clock Path Skew: -0.043ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.339ns = ( 8.506 - 4.167 ) Source Clock Delay (SCD): 4.547ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.348 4.547 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf SLICE_X47Y63 FDPE r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X47Y63 FDPE (Prop_fdpe_C_Q) 0.348 4.895 r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/Q net (fo=2, routed) 2.148 7.044 u_core/tx_inst/dac_interface_inst/dac_data_reg[7] OLOGIC_X0Y96 ODDR r u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 ------------------------------------------------------------------- ------------------- (clock clk_120m_dac fall edge) 4.167 4.167 f D13 0.000 4.167 f clk_120m_dac (IN) net (fo=0) 0.000 4.167 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 5.526 f clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 7.130 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 7.207 f u_core/bufg_120m/O net (fo=69, routed) 1.299 8.506 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf OLOGIC_X0Y96 ODDR f u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/C clock pessimism 0.165 8.670 clock uncertainty -0.061 8.609 OLOGIC_X0Y96 ODDR (Setup_oddr_C_D2) -0.844 7.765 u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data ------------------------------------------------------------------- required time 7.765 arrival time -7.044 ------------------------------------------------------------------- slack 0.722 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[0]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/reset_sync_120m_reg[1]/D (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.077ns Source Clock Delay (SCD): 1.559ns Clock Pessimism Removal (CPR): 0.518ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.637 1.559 u_core/clk_120m_dac_buf SLICE_X31Y114 FDCE r u_core/reset_sync_120m_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y114 FDCE (Prop_fdce_C_Q) 0.141 1.700 r u_core/reset_sync_120m_reg[0]/Q net (fo=1, routed) 0.055 1.755 u_core/reset_sync_120m[0] SLICE_X31Y114 FDCE r u_core/reset_sync_120m_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.909 2.077 u_core/clk_120m_dac_buf SLICE_X31Y114 FDCE r u_core/reset_sync_120m_reg[1]/C clock pessimism -0.518 1.559 SLICE_X31Y114 FDCE (Hold_fdce_C_D) 0.075 1.634 u_core/reset_sync_120m_reg[1] ------------------------------------------------------------------- required time -1.634 arrival time 1.755 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_120m_dac Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { clk_120m_dac } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.170 8.333 6.163 RAMB36_X1Y12 u_core/tx_inst/plfm_chirp_inst/long_chirp_rd_data_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X60Y64 u_core/chirp_frame_toggle_120m_reg/C High Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X60Y64 u_core/chirp_frame_toggle_120m_reg/C --------------------------------------------------------------------------------------------------- From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 11.660ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 11.660ns (required time - arrival time) Source: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 4.933ns (logic 1.003ns (20.331%) route 3.930ns (79.669%)) Logic Levels: 4 (LUT5=2 LUT6=1 MUXF7=1) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.069ns = ( 21.736 - 16.667 ) Source Clock Delay (SCD): 5.598ns Clock Pessimism Removal (CPR): 0.489ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=288, routed) 1.505 5.598 u_core/gen_ft2232h.usb_inst/CLK SLICE_X28Y120 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X28Y120 FDCE (Prop_fdce_C_Q) 0.379 5.977 r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/Q net (fo=80, routed) 2.391 8.368 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg_n_0_[0] SLICE_X10Y118 LUT5 (Prop_lut5_I4_O) 0.105 8.473 r u_core/gen_ft2232h.usb_inst/ft_data_out[2]_i_11/O net (fo=1, routed) 0.000 8.473 u_core/gen_ft2232h.usb_inst/ft_data_out[2]_i_11_n_0 SLICE_X10Y118 MUXF7 (Prop_muxf7_I0_O) 0.173 8.646 r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2]_i_5/O net (fo=1, routed) 0.717 9.363 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2]_i_5_n_0 SLICE_X8Y119 LUT6 (Prop_lut6_I5_O) 0.241 9.604 r u_core/gen_ft2232h.usb_inst/ft_data_out[2]_i_2/O net (fo=1, routed) 0.822 10.426 u_core/gen_ft2232h.usb_inst/ft_data_out[2]_i_2_n_0 SLICE_X8Y121 LUT5 (Prop_lut5_I0_O) 0.105 10.531 r u_core/gen_ft2232h.usb_inst/ft_data_out[2]_i_1/O net (fo=1, routed) 0.000 10.531 u_core/gen_ft2232h.usb_inst/ft_data_out0_in[2] SLICE_X8Y121 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=288, routed) 1.391 21.736 u_core/gen_ft2232h.usb_inst/CLK SLICE_X8Y121 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2]/C clock pessimism 0.489 22.225 clock uncertainty -0.106 22.119 SLICE_X8Y121 FDCE (Setup_fdce_C_D) 0.072 22.191 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[2] ------------------------------------------------------------------- required time 22.191 arrival time -10.531 ------------------------------------------------------------------- slack 11.660 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/reset_sync_ft601_reg[1]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.939ns Source Clock Delay (SCD): 2.292ns Clock Pessimism Removal (CPR): 0.647ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=288, routed) 0.634 2.292 u_core/ft601_clk_buf SLICE_X25Y121 FDCE r u_core/reset_sync_ft601_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y121 FDCE (Prop_fdce_C_Q) 0.141 2.433 r u_core/reset_sync_ft601_reg[0]/Q net (fo=1, routed) 0.055 2.488 u_core/reset_sync_ft601[0] SLICE_X25Y121 FDCE r u_core/reset_sync_ft601_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=288, routed) 0.906 2.939 u_core/ft601_clk_buf SLICE_X25Y121 FDCE r u_core/reset_sync_ft601_reg[1]/C clock pessimism -0.647 2.292 SLICE_X25Y121 FDCE (Hold_fdce_C_D) 0.075 2.367 u_core/reset_sync_ft601_reg[1] ------------------------------------------------------------------- required time -2.367 arrival time 2.488 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ft_clkout Waveform(ns): { 0.000 8.333 } Period(ns): 16.667 Sources: { ft_clkout } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 16.667 15.075 BUFGCTRL_X0Y1 u_core/bufg_ft601/I Low Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X24Y126 u_core/cmd_valid_toggle_ft601_reg/C High Pulse Width Slow FDCE/C n/a 0.500 8.333 7.833 SLICE_X24Y126 u_core/cmd_valid_toggle_ft601_reg/C --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.242ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.242ns (required time - arrival time) Source: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_fall_bufg_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (MaxDelay Path 2.500ns) Data Path Delay: 2.162ns (logic 0.448ns (20.724%) route 1.714ns (79.276%)) Logic Levels: 0 Timing Exception: MaxDelay Path 2.500ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- ILOGIC_X0Y16 0.000 0.000 r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C ILOGIC_X0Y16 IDDR (Prop_iddr_C_Q2) 0.448 0.448 r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/Q2 net (fo=1, routed) 1.714 2.162 u_core/rx_inst/adc/adc_data_fall[4] SLICE_X1Y54 FDRE r u_core/rx_inst/adc/adc_data_fall_bufg_reg[4]/D ------------------------------------------------------------------- ------------------- max delay 2.500 2.500 SLICE_X1Y54 FDRE (Setup_fdre_C_D) -0.096 2.404 u_core/rx_inst/adc/adc_data_fall_bufg_reg[4] ------------------------------------------------------------------- required time 2.404 arrival time -2.162 ------------------------------------------------------------------- slack 0.242 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 1.104ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.686ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.104ns (required time - arrival time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/mf_dual/buffer_read_ptr_reg[0]_rep__4/CLR (recovery check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 8.258ns (logic 0.590ns (7.144%) route 7.668ns (92.856%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.245ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.300ns = ( 14.300 - 10.000 ) Source Clock Delay (SCD): 4.704ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11820, routed) 1.505 4.704 u_core/clk_100m_buf SLICE_X29Y117 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y117 FDCE (Prop_fdce_C_Q) 0.348 5.052 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 2.643 7.695 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X2Y72 LUT1 (Prop_lut1_I0_O) 0.242 7.937 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4501, routed) 5.025 12.962 u_core/rx_inst/mf_dual/bc_reg_reg SLICE_X36Y7 FDCE f u_core/rx_inst/mf_dual/buffer_read_ptr_reg[0]_rep__4/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11820, routed) 1.260 14.300 u_core/rx_inst/mf_dual/clk_100m_buf SLICE_X36Y7 FDCE r u_core/rx_inst/mf_dual/buffer_read_ptr_reg[0]_rep__4/C clock pessimism 0.159 14.459 clock uncertainty -0.061 14.397 SLICE_X36Y7 FDCE (Recov_fdce_C_CLR) -0.331 14.066 u_core/rx_inst/mf_dual/buffer_read_ptr_reg[0]_rep__4 ------------------------------------------------------------------- required time 14.066 arrival time -12.962 ------------------------------------------------------------------- slack 1.104 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.686ns (arrival time - required time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/status_reg_reg[0]/CLR (removal check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 1.803ns (logic 0.227ns (12.592%) route 1.576ns (87.408%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.208ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.016ns Source Clock Delay (SCD): 1.557ns Clock Pessimism Removal (CPR): 0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11820, routed) 0.635 1.557 u_core/clk_100m_buf SLICE_X29Y117 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y117 FDCE (Prop_fdce_C_Q) 0.128 1.685 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 1.373 3.058 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X2Y72 LUT1 (Prop_lut1_I0_O) 0.099 3.157 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4501, routed) 0.203 3.360 u_core/adc/mmcm_inst/RST0 SLICE_X0Y72 FDCE f u_core/status_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11820, routed) 0.849 2.016 u_core/clk_100m_buf SLICE_X0Y72 FDCE r u_core/status_reg_reg[0]/C clock pessimism -0.251 1.765 SLICE_X0Y72 FDCE (Remov_fdce_C_CLR) -0.092 1.673 u_core/status_reg_reg[0] ------------------------------------------------------------------- required time -1.673 arrival time 3.360 ------------------------------------------------------------------- slack 1.686 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 3.585ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.278ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.585ns (required time - arrival time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/current_state_reg[0]/CLR (recovery check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 4.165ns (logic 0.590ns (14.165%) route 3.575ns (85.835%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.191ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.351ns = ( 12.684 - 8.333 ) Source Clock Delay (SCD): 4.706ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.507 4.706 u_core/clk_120m_dac_buf SLICE_X31Y114 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y114 FDCE (Prop_fdce_C_Q) 0.348 5.054 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.476 5.530 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X34Y114 LUT1 (Prop_lut1_I0_O) 0.242 5.772 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 3.099 8.871 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X58Y63 FDCE f u_core/tx_inst/plfm_chirp_inst/current_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.310 12.684 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X58Y63 FDCE r u_core/tx_inst/plfm_chirp_inst/current_state_reg[0]/C clock pessimism 0.165 12.848 clock uncertainty -0.061 12.787 SLICE_X58Y63 FDCE (Recov_fdce_C_CLR) -0.331 12.456 u_core/tx_inst/plfm_chirp_inst/current_state_reg[0] ------------------------------------------------------------------- required time 12.456 arrival time -8.871 ------------------------------------------------------------------- slack 3.585 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.278ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/CLR (removal check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 1.404ns (logic 0.227ns (16.169%) route 1.177ns (83.831%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.217ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.027ns Source Clock Delay (SCD): 1.559ns Clock Pessimism Removal (CPR): 0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.637 1.559 u_core/clk_120m_dac_buf SLICE_X31Y114 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X31Y114 FDCE (Prop_fdce_C_Q) 0.128 1.687 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.199 1.886 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X34Y114 LUT1 (Prop_lut1_I0_O) 0.099 1.985 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 0.978 2.963 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X58Y93 FDCE f u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.860 2.027 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X58Y93 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/C clock pessimism -0.251 1.777 SLICE_X58Y93 FDCE (Remov_fdce_C_CLR) -0.092 1.685 u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1] ------------------------------------------------------------------- required time -1.685 arrival time 2.963 ------------------------------------------------------------------- slack 1.278 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.360ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.279ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.360ns (required time - arrival time) Source: u_core/rx_inst/adc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/PRE (recovery check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.819ns (logic 0.630ns (34.629%) route 1.189ns (65.371%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.290ns = ( 4.790 - 2.500 ) Source Clock Delay (SCD): 2.351ns Clock Pessimism Removal (CPR): 0.085ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.118 0.713 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.081 0.794 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.133 0.927 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 1.008 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 1.343 2.351 u_core/rx_inst/adc/clk_400m SLICE_X12Y72 FDCE r u_core/rx_inst/adc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X12Y72 FDCE (Prop_fdce_C_Q) 0.398 2.749 r u_core/rx_inst/adc/reset_sync_400m_reg[1]/Q net (fo=1, routed) 0.360 3.109 u_core/rx_inst/adc/reset_sync_400m[1] SLICE_X12Y72 LUT1 (Prop_lut1_I0_O) 0.232 3.341 f u_core/rx_inst/adc/dco_phase_i_2/O net (fo=10, routed) 0.830 4.170 u_core/rx_inst/adc/dco_phase_i_2_n_0 SLICE_X1Y75 FDPE f u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/PRE ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.112 3.209 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.286 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.126 3.412 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.489 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 1.301 4.790 u_core/rx_inst/adc/clk_400m SLICE_X1Y75 FDPE r u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv/C clock pessimism 0.085 4.875 clock uncertainty -0.053 4.822 SLICE_X1Y75 FDPE (Recov_fdpe_C_PRE) -0.292 4.530 u_core/rx_inst/adc/adc_data_400m_reg_reg[7]_inv ------------------------------------------------------------------- required time 4.530 arrival time -4.170 ------------------------------------------------------------------- slack 0.360 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.279ns (arrival time - required time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[10]/CLR (removal check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.598ns (logic 0.227ns (37.986%) route 0.371ns (62.014%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.411ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.167ns Source Clock Delay (SCD): 0.948ns Clock Pessimism Removal (CPR): -0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.643 0.948 u_core/rx_inst/ddc/bufg_clk400m_0_repN_1_alias SLICE_X41Y104 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X41Y104 FDCE (Prop_fdce_C_Q) 0.128 1.076 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=6, routed) 0.107 1.182 u_core/rx_inst/ddc/cic_i_inst/out[0] SLICE_X41Y104 LUT1 (Prop_lut1_I0_O) 0.099 1.281 f u_core/rx_inst/ddc/cic_i_inst/reset_n_400m_inst_replica_1/O net (fo=222, routed) 0.264 1.545 u_core/rx_inst/ddc/nco_core/p_0_in__0_repN_1_alias SLICE_X37Y100 FDCE f u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y14 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica_1/O net (fo=3, routed) 0.033 0.146 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN_1 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.175 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=1, routed) 0.046 0.221 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.250 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=742, routed) 0.917 1.167 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X37Y100 FDCE r u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[10]/C clock pessimism 0.192 1.359 SLICE_X37Y100 FDCE (Remov_fdce_C_CLR) -0.092 1.267 u_core/rx_inst/ddc/nco_core/cos_neg_reg_reg[10] ------------------------------------------------------------------- required time -1.267 arrival time 1.545 ------------------------------------------------------------------- slack 0.279 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 13.228ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.698ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 13.228ns (required time - arrival time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_real_cap_reg[13]/CLR (recovery check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 2.805ns (logic 0.592ns (21.102%) route 2.213ns (78.898%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.074ns = ( 21.741 - 16.667 ) Source Clock Delay (SCD): 5.597ns Clock Pessimism Removal (CPR): 0.489ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=288, routed) 1.504 5.597 u_core/ft601_clk_buf SLICE_X25Y121 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y121 FDCE (Prop_fdce_C_Q) 0.348 5.945 r u_core/reset_sync_ft601_reg[2]/Q net (fo=2, routed) 0.207 6.152 u_core/gen_ft2232h.usb_inst/out[0] SLICE_X25Y121 LUT1 (Prop_lut1_I0_O) 0.244 6.396 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=165, routed) 2.006 8.402 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X9Y117 FDCE f u_core/gen_ft2232h.usb_inst/doppler_real_cap_reg[13]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=288, routed) 1.396 21.741 u_core/gen_ft2232h.usb_inst/CLK SLICE_X9Y117 FDCE r u_core/gen_ft2232h.usb_inst/doppler_real_cap_reg[13]/C clock pessimism 0.489 22.230 clock uncertainty -0.106 22.124 SLICE_X9Y117 FDCE (Recov_fdce_C_CLR) -0.494 21.630 u_core/gen_ft2232h.usb_inst/doppler_real_cap_reg[13] ------------------------------------------------------------------- required time 21.630 arrival time -8.402 ------------------------------------------------------------------- slack 13.228 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.698ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/CLR (removal check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.555ns (logic 0.232ns (41.776%) route 0.323ns (58.224%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.939ns Source Clock Delay (SCD): 2.292ns Clock Pessimism Removal (CPR): 0.633ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=288, routed) 0.634 2.292 u_core/ft601_clk_buf SLICE_X25Y121 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y121 FDCE (Prop_fdce_C_Q) 0.128 2.420 r u_core/reset_sync_ft601_reg[2]/Q net (fo=2, routed) 0.083 2.504 u_core/gen_ft2232h.usb_inst/out[0] SLICE_X25Y121 LUT1 (Prop_lut1_I0_O) 0.104 2.608 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=165, routed) 0.240 2.847 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X27Y121 FDCE f u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=288, routed) 0.906 2.939 u_core/gen_ft2232h.usb_inst/CLK SLICE_X27Y121 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/C clock pessimism -0.633 2.306 SLICE_X27Y121 FDCE (Remov_fdce_C_CLR) -0.157 2.149 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1] ------------------------------------------------------------------- required time -2.149 arrival time 2.847 ------------------------------------------------------------------- slack 0.698