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released this
2026-04-13 13:39:11 +00:00 | 69 commits to main since this release📅 Originally published on GitHub: Mon, 13 Apr 2026 13:39:56 GMT
🏷️ Git tag created: Mon, 13 Apr 2026 13:39:11 GMTAERIS-10 50T AGC Bitstream — Hybrid AGC + Timing Fix
Vivado Build 16 bitstream for the XC7A50T-FTG256 production board. Adds hybrid AGC (FPGA inner loop) with 5 new host registers (0x28–0x2C) and a 45x timing margin improvement over the previous build.
Timing
Metric Value WNS +0.045 ns WHS +0.058 ns WPWS +0.361 ns Failing Endpoints 0 All constraints met Yes Utilization (xc7a50tftg256-2)
Resource Used Available Util% LUTs 10,235 32,600 31.4% Flip-Flops 12,729 65,200 19.5% BRAM 17.5 75 23.3% DSP48E1 112 120 93.3% IOB 82 170 48.2% What Changed (from v1.0.0-ft2232h)
- AGC Phase 1:
rx_gain_control.vrewritten — per-frame peak/saturation tracking, auto-shift with attack/decay/holdoff, signed gain ±7 (±42 dB) - AGC Phase 2: New registers 0x28–0x2C (
agc_enable,agc_target,agc_attack,agc_decay,agc_holdoff) inradar_system_top.v - AGC Phase 3:
status_words[4]carries AGC metrics (gain, peak magnitude, saturation count, enable). DIG_5 GPIO (H11) outputs saturation flag for STM32 outer loop. Both USB interfaces (FT601 + FT2232H) updated. - Timing fix: CIC
max_fanout4→16, +200 ps setup uncertainty on 400 MHz domain,ExtraNetDelay_highplacement +AggressiveExplorerouting - GUI Phase 6: AGC opcodes + status parsing in
radar_protocol.py. AGC control groups in both tkinter and V7 PyQt dashboards. 11 new AGC tests. - Cross-layer: AGC opcodes/defaults/status assertions added.
contract_parser.pycomment-stripping fix. - CI: 157 tests passing (103 Python GUI + 25 FPGA iverilog + 29 cross-layer)
Assets
radar_system_top_50t.bit— Production bitstream (program via Vivado/xsdb)02_timing_summary.rpt— Post-route timing report04_utilization.rpt— Post-route utilization report
Build Environment
- Vivado 2025.2 (lin64)
- Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
- Top module:
radar_system_top_50t
Downloads
- AGC Phase 1: