Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Mon Apr 13 16:10:24 2026 | Host : jason-pc running 64-bit Ubuntu 25.10 | Command : report_timing_summary -file /home/jason-stone/PLFM_RADAR/9_Firmware/9_2_FPGA/build_50t/reports_50t/02_timing_summary.rpt | Design : radar_system_top_50t | Device : 7a50t-ftg256 | Speed File : -2 PRODUCTION 1.23 2018-06-13 | Design State : Physopt postRoute --------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (15) 6. checking no_output_delay (27) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (15) ------------------------------- There are 11 input ports with no input delay specified. (HIGH) There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (27) -------------------------------- There are 27 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.045 0.000 0 37046 0.058 0.000 0 37022 0.361 0.000 0 12983 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- adc_dco_p {0.000 1.250} 2.500 400.000 clk_mmcm_fb_out {0.000 1.250} 2.500 400.000 clk_mmcm_out0 {0.000 1.250} 2.500 400.000 clk_100m {0.000 5.000} 10.000 100.000 clk_120m_dac {0.000 4.167} 8.333 120.005 ft_clkout {0.000 8.334} 16.667 59.999 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- adc_dco_p 0.920 0.000 0 8 0.361 0.000 0 10 clk_mmcm_fb_out 0.908 0.000 0 3 clk_mmcm_out0 0.078 0.000 0 3101 0.074 0.000 0 3101 0.684 0.000 0 711 clk_100m 0.530 0.000 0 31211 0.058 0.000 0 31211 3.870 0.000 0 11878 clk_120m_dac 1.062 0.000 0 102 0.121 0.000 0 102 3.666 0.000 0 70 ft_clkout 10.421 0.000 0 370 0.121 0.000 0 370 7.833 0.000 0 311 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- adc_dco_p clk_mmcm_out0 0.045 0.000 0 16 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_100m clk_100m 0.636 0.000 0 1580 2.509 0.000 0 1580 **async_default** clk_120m_dac clk_120m_dac 3.788 0.000 0 45 0.806 0.000 0 45 **async_default** clk_mmcm_out0 clk_mmcm_out0 0.382 0.000 0 306 0.273 0.000 0 306 **async_default** ft_clkout ft_clkout 9.845 0.000 0 307 0.846 0.000 0 307 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: adc_dco_p Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: adc_d_p[4] (input port clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: adc_dco_p Path Type: Setup (Max at Fast Process Corner) Requirement: 1.250ns (adc_dco_p rise@2.500ns - adc_dco_p fall@1.250ns) Data Path Delay: 0.450ns (logic 0.450ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUFDS=1) Input Delay: 1.000ns Clock Path Skew: 1.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.167ns = ( 3.667 - 2.500 ) Source Clock Delay (SCD): 0.000ns = ( 1.250 - 1.250 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.043ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.050ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock adc_dco_p fall edge) 1.250 1.250 f input delay 1.000 2.250 R10 0.000 2.250 r adc_d_p[4] (IN) net (fo=0) 0.000 2.250 u_core/rx_inst/adc/adc_d_p[4] R10 IBUFDS (Prop_ibufds_I_O) 0.450 2.700 r u_core/rx_inst/adc/data_buffers[4].ibufds_data/O net (fo=1, routed) 0.000 2.700 u_core/rx_inst/adc/adc_data_4 ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D ------------------------------------------------------------------- ------------------- (clock adc_dco_p rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 2.913 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.179 3.092 u_core/rx_inst/adc/adc_dco BUFIO_X0Y2 BUFIO (Prop_bufio_I_O) 0.484 3.576 r u_core/rx_inst/adc/bufio_dco/O net (fo=8, routed) 0.091 3.667 u_core/rx_inst/adc/adc_dco_bufio ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C clock pessimism 0.000 3.667 clock uncertainty -0.043 3.624 ILOGIC_X0Y16 IDDR (Setup_iddr_C_D) -0.003 3.621 u_core/rx_inst/adc/iddr_gen[4].iddr_inst ------------------------------------------------------------------- required time 3.621 arrival time -2.700 ------------------------------------------------------------------- slack 0.920 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: adc_dco_p Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { adc_dco_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDDR/C n/a 1.474 2.500 1.026 ILOGIC_X0Y34 u_core/rx_inst/adc/iddr_gen[0].iddr_inst/C Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_fb_out To Clock: clk_mmcm_fb_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.908ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_fb_out Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 2.500 0.908 BUFGCTRL_X0Y2 u_core/rx_inst/adc/mmcm_inst/bufg_feedback/I Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.078ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.074ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.684ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.078ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_i_inst/comb_reg[4]/RSTB (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 2.095ns (logic 0.590ns (28.159%) route 1.505ns (71.841%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.184ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.132ns = ( 4.632 - 2.500 ) Source Clock Delay (SCD): 1.945ns Clock Pessimism Removal (CPR): -0.002ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 1.350 1.945 u_core/rx_inst/ddc/bufg_clk400m_0_repN_alias SLICE_X36Y88 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y88 FDCE (Prop_fdce_C_Q) 0.348 2.293 f u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=4, routed) 0.153 2.446 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X36Y88 LUT1 (Prop_lut1_I0_O) 0.242 2.688 r u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=666, routed) 1.352 4.040 u_core/rx_inst/ddc/cic_i_inst/p_0_in__0 DSP48_X1Y38 DSP48E1 r u_core/rx_inst/ddc/cic_i_inst/comb_reg[4]/RSTB ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.126 3.223 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.300 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=706, routed) 1.332 4.632 u_core/rx_inst/ddc/cic_i_inst/clk_400m DSP48_X1Y38 DSP48E1 r u_core/rx_inst/ddc/cic_i_inst/comb_reg[4]/CLK clock pessimism -0.002 4.630 clock uncertainty -0.053 4.576 DSP48_X1Y38 DSP48E1 (Setup_dsp48e1_CLK_RSTB) -0.458 4.118 u_core/rx_inst/ddc/cic_i_inst/comb_reg[4] ------------------------------------------------------------------- required time 4.118 arrival time -4.040 ------------------------------------------------------------------- slack 0.078 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.074ns (arrival time - required time) Source: u_core/rx_inst/ddc/cic_q_inst/integrator_sampled_comb_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][3]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.328ns (logic 0.128ns (39.042%) route 0.200ns (60.958%)) Logic Levels: 0 Clock Path Skew: 0.260ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.011ns Source Clock Delay (SCD): 0.931ns Clock Pessimism Removal (CPR): -0.180ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.042 0.347 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.373 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=706, routed) 0.559 0.931 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X39Y88 FDRE r u_core/rx_inst/ddc/cic_q_inst/integrator_sampled_comb_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y88 FDRE (Prop_fdre_C_Q) 0.128 1.059 r u_core/rx_inst/ddc/cic_q_inst/integrator_sampled_comb_reg[3]/Q net (fo=2, routed) 0.200 1.259 u_core/rx_inst/ddc/cic_q_inst/integrator_sampled_comb[3] SLICE_X35Y85 FDRE r u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][3]/D ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.046 0.159 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.188 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=706, routed) 0.823 1.011 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X35Y85 FDRE r u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][3]/C clock pessimism 0.180 1.191 SLICE_X35Y85 FDRE (Hold_fdre_C_D) -0.006 1.185 u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][3] ------------------------------------------------------------------- required time -1.185 arrival time 1.259 ------------------------------------------------------------------- slack 0.074 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_out0 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 1.816 2.500 0.684 DSP48_X1Y44 u_core/rx_inst/ddc/dsp_mixer_i/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 Low Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X41Y79 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X41Y79 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.530ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.530ns (required time - arrival time) Source: u_core/rx_inst/mf_dual/input_buffer_i_reg/CLKBWRCLK (rising edge-triggered cell RAMB18E1 clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/mf_dual/overlap_cache_i_reg[65][14]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.257ns (logic 2.125ns (22.956%) route 7.132ns (77.044%)) Logic Levels: 0 Clock Path Skew: -0.125ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.300ns = ( 14.300 - 10.000 ) Source Clock Delay (SCD): 4.584ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11893, routed) 1.385 4.584 u_core/rx_inst/mf_dual/clk_100m_buf RAMB18_X1Y32 RAMB18E1 r u_core/rx_inst/mf_dual/input_buffer_i_reg/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB18_X1Y32 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[14]) 2.125 6.709 r u_core/rx_inst/mf_dual/input_buffer_i_reg/DOBDO[14] net (fo=129, routed) 7.132 13.840 u_core/rx_inst/mf_dual/buf_rdata_i[14] SLICE_X46Y39 FDRE r u_core/rx_inst/mf_dual/overlap_cache_i_reg[65][14]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11893, routed) 1.260 14.300 u_core/rx_inst/mf_dual/clk_100m_buf SLICE_X46Y39 FDRE r u_core/rx_inst/mf_dual/overlap_cache_i_reg[65][14]/C clock pessimism 0.159 14.459 clock uncertainty -0.061 14.397 SLICE_X46Y39 FDRE (Setup_fdre_C_D) -0.027 14.370 u_core/rx_inst/mf_dual/overlap_cache_i_reg[65][14] ------------------------------------------------------------------- required time 14.370 arrival time -13.840 ------------------------------------------------------------------- slack 0.530 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.058ns (arrival time - required time) Source: u_core/rx_inst/doppler_proc/mem_wdata_i_reg[12]/C (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/doppler_proc/doppler_i_mem_reg/DIADI[12] (rising edge-triggered cell RAMB36E1 clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 0.268ns (logic 0.164ns (61.116%) route 0.104ns (38.884%)) Logic Levels: 0 Clock Path Skew: 0.056ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.039ns Source Clock Delay (SCD): 1.483ns Clock Pessimism Removal (CPR): 0.499ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11893, routed) 0.562 1.483 u_core/rx_inst/doppler_proc/clk_100m_buf SLICE_X8Y96 FDRE r u_core/rx_inst/doppler_proc/mem_wdata_i_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y96 FDRE (Prop_fdre_C_Q) 0.164 1.647 r u_core/rx_inst/doppler_proc/mem_wdata_i_reg[12]/Q net (fo=1, routed) 0.104 1.752 u_core/rx_inst/doppler_proc/mem_wdata_i[12] RAMB36_X0Y19 RAMB36E1 r u_core/rx_inst/doppler_proc/doppler_i_mem_reg/DIADI[12] ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11893, routed) 0.871 2.039 u_core/rx_inst/doppler_proc/clk_100m_buf RAMB36_X0Y19 RAMB36E1 r u_core/rx_inst/doppler_proc/doppler_i_mem_reg/CLKARDCLK clock pessimism -0.499 1.539 RAMB36_X0Y19 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[12]) 0.155 1.694 u_core/rx_inst/doppler_proc/doppler_i_mem_reg ------------------------------------------------------------------- required time -1.694 arrival time 1.752 ------------------------------------------------------------------- slack 0.058 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100m Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100m } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.272 10.000 6.728 DSP48_X1Y0 u_core/rx_inst/ddc/fir_i_inst/mult_reg_reg[0]/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X10Y65 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X10Y65 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 1.062ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.062ns (required time - arrival time) Source: u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C (rising edge-triggered cell FDPE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 (falling edge-triggered cell ODDR clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (clk_120m_dac fall@4.167ns - clk_120m_dac rise@0.000ns) Data Path Delay: 2.140ns (logic 0.348ns (16.258%) route 1.792ns (83.742%)) Logic Levels: 0 Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.339ns = ( 8.506 - 4.167 ) Source Clock Delay (SCD): 4.622ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.423 4.622 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf SLICE_X0Y52 FDPE r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y52 FDPE (Prop_fdpe_C_Q) 0.348 4.970 r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]/Q net (fo=2, routed) 1.792 6.763 u_core/tx_inst/dac_interface_inst/dac_data_reg[7] OLOGIC_X0Y96 ODDR r u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/D2 ------------------------------------------------------------------- ------------------- (clock clk_120m_dac fall edge) 4.167 4.167 f D13 0.000 4.167 f clk_120m_dac (IN) net (fo=0) 0.000 4.167 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 5.526 f clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 7.130 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 7.207 f u_core/bufg_120m/O net (fo=69, routed) 1.299 8.506 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf OLOGIC_X0Y96 ODDR f u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data/C clock pessimism 0.224 8.730 clock uncertainty -0.061 8.668 OLOGIC_X0Y96 ODDR (Setup_oddr_C_D2) -0.844 7.824 u_core/tx_inst/dac_interface_inst/oddr_dac_data_gen[7].oddr_dac_data ------------------------------------------------------------------- required time 7.824 arrival time -6.763 ------------------------------------------------------------------- slack 1.062 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[0]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/reset_sync_120m_reg[1]/D (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.024ns Source Clock Delay (SCD): 1.509ns Clock Pessimism Removal (CPR): 0.515ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.587 1.509 u_core/clk_120m_dac_buf SLICE_X1Y63 FDCE r u_core/reset_sync_120m_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y63 FDCE (Prop_fdce_C_Q) 0.141 1.650 r u_core/reset_sync_120m_reg[0]/Q net (fo=1, routed) 0.055 1.705 u_core/reset_sync_120m[0] SLICE_X1Y63 FDCE r u_core/reset_sync_120m_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.856 2.024 u_core/clk_120m_dac_buf SLICE_X1Y63 FDCE r u_core/reset_sync_120m_reg[1]/C clock pessimism -0.515 1.509 SLICE_X1Y63 FDCE (Hold_fdce_C_D) 0.075 1.584 u_core/reset_sync_120m_reg[1] ------------------------------------------------------------------- required time -1.584 arrival time 1.705 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_120m_dac Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { clk_120m_dac } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.170 8.333 6.163 RAMB36_X0Y10 u_core/tx_inst/plfm_chirp_inst/long_chirp_rd_data_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.500 4.167 3.667 SLICE_X1Y50 u_core/chirp_frame_toggle_120m_reg/C High Pulse Width Slow FDCE/C n/a 0.500 4.166 3.666 SLICE_X1Y50 u_core/chirp_frame_toggle_120m_reg/C --------------------------------------------------------------------------------------------------- From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 10.421ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.421ns (required time - arrival time) Source: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/ft_data_out_reg[1]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 6.132ns (logic 0.694ns (11.318%) route 5.438ns (88.682%)) Logic Levels: 3 (LUT5=1 LUT6=2) Clock Path Skew: -0.040ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.052ns = ( 21.719 - 16.667 ) Source Clock Delay (SCD): 5.581ns Clock Pessimism Removal (CPR): 0.489ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.536 3.992 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.073 r u_core/bufg_ft601/O net (fo=310, routed) 1.508 5.581 u_core/gen_ft2232h.usb_inst/CLK SLICE_X26Y118 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X26Y118 FDCE (Prop_fdce_C_Q) 0.379 5.960 r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[0]/Q net (fo=82, routed) 2.687 8.647 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg_n_0_[0] SLICE_X9Y84 LUT5 (Prop_lut5_I3_O) 0.105 8.752 r u_core/gen_ft2232h.usb_inst/ft_data_out[1]_i_9/O net (fo=1, routed) 1.932 10.684 u_core/gen_ft2232h.usb_inst/ft_data_out[1]_i_9_n_0 SLICE_X10Y120 LUT6 (Prop_lut6_I5_O) 0.105 10.789 r u_core/gen_ft2232h.usb_inst/ft_data_out[1]_i_4/O net (fo=1, routed) 0.818 11.608 u_core/gen_ft2232h.usb_inst/ft_data_out[1]_i_4_n_0 SLICE_X16Y119 LUT6 (Prop_lut6_I5_O) 0.105 11.713 r u_core/gen_ft2232h.usb_inst/ft_data_out[1]_i_1/O net (fo=1, routed) 0.000 11.713 u_core/gen_ft2232h.usb_inst/ft_data_out0_in[1] SLICE_X16Y119 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.192 20.249 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.326 r u_core/bufg_ft601/O net (fo=310, routed) 1.394 21.719 u_core/gen_ft2232h.usb_inst/CLK SLICE_X16Y119 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[1]/C clock pessimism 0.489 22.208 clock uncertainty -0.106 22.102 SLICE_X16Y119 FDCE (Setup_fdce_C_D) 0.032 22.134 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[1] ------------------------------------------------------------------- required time 22.134 arrival time -11.713 ------------------------------------------------------------------- slack 10.421 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.921ns Source Clock Delay (SCD): 2.273ns Clock Pessimism Removal (CPR): 0.647ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.320 1.612 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.638 r u_core/bufg_ft601/O net (fo=310, routed) 0.635 2.273 u_core/gen_ft2232h.usb_inst/CLK SLICE_X25Y120 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X25Y120 FDCE (Prop_fdce_C_Q) 0.141 2.414 r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/Q net (fo=1, routed) 0.055 2.470 u_core/gen_ft2232h.usb_inst/doppler_toggle_sync[0] SLICE_X25Y120 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.504 1.985 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.014 r u_core/bufg_ft601/O net (fo=310, routed) 0.907 2.921 u_core/gen_ft2232h.usb_inst/CLK SLICE_X25Y120 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/C clock pessimism -0.647 2.273 SLICE_X25Y120 FDCE (Hold_fdce_C_D) 0.075 2.348 u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1] ------------------------------------------------------------------- required time -2.348 arrival time 2.470 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ft_clkout Waveform(ns): { 0.000 8.333 } Period(ns): 16.667 Sources: { ft_clkout } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 16.667 15.075 BUFGCTRL_X0Y1 u_core/bufg_ft601/I Low Pulse Width Slow FDCE/C n/a 0.500 8.333 7.833 SLICE_X23Y126 u_core/cmd_valid_toggle_ft601_reg/C High Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X23Y126 u_core/cmd_valid_toggle_ft601_reg/C --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.045ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.045ns (required time - arrival time) Source: u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_fall_bufg_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (MaxDelay Path 2.500ns) Data Path Delay: 2.394ns (logic 0.448ns (18.715%) route 1.946ns (81.285%)) Logic Levels: 0 Timing Exception: MaxDelay Path 2.500ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- ILOGIC_X0Y2 0.000 0.000 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C ILOGIC_X0Y2 IDDR (Prop_iddr_C_Q2) 0.448 0.448 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/Q2 net (fo=1, routed) 1.946 2.394 u_core/rx_inst/adc/adc_data_fall[7] SLICE_X12Y53 FDRE r u_core/rx_inst/adc/adc_data_fall_bufg_reg[7]/D ------------------------------------------------------------------- ------------------- max delay 2.500 2.500 SLICE_X12Y53 FDRE (Setup_fdre_C_D) -0.061 2.439 u_core/rx_inst/adc/adc_data_fall_bufg_reg[7] ------------------------------------------------------------------- required time 2.439 arrival time -2.394 ------------------------------------------------------------------- slack 0.045 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.636ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 2.509ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.636ns (required time - arrival time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/self_test_inst/bram_addr_reg[1]/CLR (recovery check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.042ns (logic 0.590ns (6.525%) route 8.452ns (93.475%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.071ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.509ns = ( 14.509 - 10.000 ) Source Clock Delay (SCD): 4.603ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11893, routed) 1.404 4.603 u_core/clk_100m_buf SLICE_X0Y74 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDCE (Prop_fdce_C_Q) 0.348 4.951 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 2.904 7.855 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X47Y32 LUT1 (Prop_lut1_I0_O) 0.242 8.097 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4574, routed) 5.548 13.645 u_core/self_test_inst/RST0 SLICE_X4Y144 FDCE f u_core/self_test_inst/bram_addr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11893, routed) 1.469 14.509 u_core/self_test_inst/clk_100m_buf SLICE_X4Y144 FDCE r u_core/self_test_inst/bram_addr_reg[1]/C clock pessimism 0.165 14.674 clock uncertainty -0.061 14.612 SLICE_X4Y144 FDCE (Recov_fdce_C_CLR) -0.331 14.281 u_core/self_test_inst/bram_addr_reg[1] ------------------------------------------------------------------- required time 14.281 arrival time -13.645 ------------------------------------------------------------------- slack 0.636 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.509ns (arrival time - required time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/gain_ctrl/data_i_out_reg[6]/CLR (removal check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 2.455ns (logic 0.227ns (9.245%) route 2.228ns (90.755%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.992ns Source Clock Delay (SCD): 1.499ns Clock Pessimism Removal (CPR): 0.479ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11893, routed) 0.578 1.499 u_core/clk_100m_buf SLICE_X0Y74 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X0Y74 FDCE (Prop_fdce_C_Q) 0.128 1.627 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 1.484 3.112 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X47Y32 LUT1 (Prop_lut1_I0_O) 0.099 3.211 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4574, routed) 0.744 3.955 u_core/rx_inst/gain_ctrl/saturation_count_reg[7]_1 SLICE_X14Y66 FDCE f u_core/rx_inst/gain_ctrl/data_i_out_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11893, routed) 0.825 1.992 u_core/rx_inst/gain_ctrl/clk_100m_buf SLICE_X14Y66 FDCE r u_core/rx_inst/gain_ctrl/data_i_out_reg[6]/C clock pessimism -0.479 1.512 SLICE_X14Y66 FDCE (Remov_fdce_C_CLR) -0.067 1.445 u_core/rx_inst/gain_ctrl/data_i_out_reg[6] ------------------------------------------------------------------- required time -1.445 arrival time 3.955 ------------------------------------------------------------------- slack 2.509 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 3.788ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.806ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.788ns (required time - arrival time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/CLR (recovery check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 4.065ns (logic 0.590ns (14.514%) route 3.475ns (85.486%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.088ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.371ns = ( 12.704 - 8.333 ) Source Clock Delay (SCD): 4.617ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.418 4.617 u_core/clk_120m_dac_buf SLICE_X1Y63 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y63 FDCE (Prop_fdce_C_Q) 0.348 4.965 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.685 5.650 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X1Y63 LUT1 (Prop_lut1_I0_O) 0.242 5.892 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 2.790 8.682 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X5Y46 FDCE f u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.331 12.704 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X5Y46 FDCE r u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/C clock pessimism 0.159 12.863 clock uncertainty -0.061 12.802 SLICE_X5Y46 FDCE (Recov_fdce_C_CLR) -0.331 12.471 u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1] ------------------------------------------------------------------- required time 12.471 arrival time -8.682 ------------------------------------------------------------------- slack 3.788 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.806ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[4]/CLR (removal check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.729ns (logic 0.227ns (31.149%) route 0.502ns (68.851%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.024ns Source Clock Delay (SCD): 1.509ns Clock Pessimism Removal (CPR): 0.500ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.587 1.509 u_core/clk_120m_dac_buf SLICE_X1Y63 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y63 FDCE (Prop_fdce_C_Q) 0.128 1.637 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.279 1.916 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X1Y63 LUT1 (Prop_lut1_I0_O) 0.099 2.015 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 0.223 2.238 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X0Y64 FDCE f u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.856 2.024 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X0Y64 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[4]/C clock pessimism -0.500 1.524 SLICE_X0Y64 FDCE (Remov_fdce_C_CLR) -0.092 1.432 u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[4] ------------------------------------------------------------------- required time -1.432 arrival time 2.238 ------------------------------------------------------------------- slack 0.806 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.382ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.273ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.382ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/quadrant_pipe_reg[0]/CLR (recovery check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.825ns (logic 0.590ns (32.325%) route 1.235ns (67.675%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.038ns = ( 4.538 - 2.500 ) Source Clock Delay (SCD): 1.945ns Clock Pessimism Removal (CPR): -0.002ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 1.350 1.945 u_core/rx_inst/ddc/bufg_clk400m_0_repN_alias SLICE_X36Y88 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y88 FDCE (Prop_fdce_C_Q) 0.348 2.293 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=4, routed) 0.153 2.446 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X36Y88 LUT1 (Prop_lut1_I0_O) 0.242 2.688 f u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=666, routed) 1.082 3.770 u_core/rx_inst/ddc/nco_core/p_0_in__0 SLICE_X40Y82 FDCE f u_core/rx_inst/ddc/nco_core/quadrant_pipe_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.126 3.223 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.300 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=706, routed) 1.238 4.538 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X40Y82 FDCE r u_core/rx_inst/ddc/nco_core/quadrant_pipe_reg[0]/C clock pessimism -0.002 4.536 clock uncertainty -0.053 4.483 SLICE_X40Y82 FDCE (Recov_fdce_C_CLR) -0.331 4.152 u_core/rx_inst/ddc/nco_core/quadrant_pipe_reg[0] ------------------------------------------------------------------- required time 4.152 arrival time -3.770 ------------------------------------------------------------------- slack 0.382 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.273ns (arrival time - required time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/sin_out_reg[11]/CLR (removal check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.550ns (logic 0.227ns (41.306%) route 0.323ns (58.694%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.344ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.015ns Source Clock Delay (SCD): 0.863ns Clock Pessimism Removal (CPR): -0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.559 0.863 u_core/rx_inst/ddc/bufg_clk400m_0_repN_alias SLICE_X36Y88 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X36Y88 FDCE (Prop_fdce_C_Q) 0.128 0.991 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=4, routed) 0.089 1.080 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X36Y88 LUT1 (Prop_lut1_I0_O) 0.099 1.179 f u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=666, routed) 0.234 1.413 u_core/rx_inst/ddc/nco_core/p_0_in__0 SLICE_X38Y88 FDCE f u_core/rx_inst/ddc/nco_core/sin_out_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.046 0.159 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.188 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=706, routed) 0.827 1.015 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X38Y88 FDCE r u_core/rx_inst/ddc/nco_core/sin_out_reg[11]/C clock pessimism 0.192 1.207 SLICE_X38Y88 FDCE (Remov_fdce_C_CLR) -0.067 1.140 u_core/rx_inst/ddc/nco_core/sin_out_reg[11] ------------------------------------------------------------------- required time -1.140 arrival time 1.413 ------------------------------------------------------------------- slack 0.273 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 9.845ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.846ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 9.845ns (required time - arrival time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_words_reg[2][16]/CLR (recovery check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 6.372ns (logic 0.587ns (9.212%) route 5.785ns (90.788%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.012ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.046ns = ( 21.713 - 16.667 ) Source Clock Delay (SCD): 5.480ns Clock Pessimism Removal (CPR): 0.421ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.536 3.992 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.073 r u_core/bufg_ft601/O net (fo=310, routed) 1.407 5.480 u_core/ft601_clk_buf SLICE_X1Y74 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y74 FDCE (Prop_fdce_C_Q) 0.348 5.828 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.678 6.506 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X1Y75 LUT1 (Prop_lut1_I0_O) 0.239 6.745 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 5.108 11.853 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X24Y123 FDCE f u_core/gen_ft2232h.usb_inst/status_words_reg[2][16]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.192 20.249 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.326 r u_core/bufg_ft601/O net (fo=310, routed) 1.388 21.713 u_core/gen_ft2232h.usb_inst/CLK SLICE_X24Y123 FDCE r u_core/gen_ft2232h.usb_inst/status_words_reg[2][16]/C clock pessimism 0.421 22.135 clock uncertainty -0.106 22.029 SLICE_X24Y123 FDCE (Recov_fdce_C_CLR) -0.331 21.698 u_core/gen_ft2232h.usb_inst/status_words_reg[2][16] ------------------------------------------------------------------- required time 21.698 arrival time -11.853 ------------------------------------------------------------------- slack 9.845 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.846ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[0]/CLR (removal check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 1.105ns (logic 0.226ns (20.444%) route 0.879ns (79.556%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.351ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.950ns Source Clock Delay (SCD): 2.218ns Clock Pessimism Removal (CPR): 0.380ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.320 1.612 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.638 r u_core/bufg_ft601/O net (fo=310, routed) 0.580 2.218 u_core/ft601_clk_buf SLICE_X1Y74 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y74 FDCE (Prop_fdce_C_Q) 0.128 2.346 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.299 2.645 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X1Y75 LUT1 (Prop_lut1_I0_O) 0.098 2.743 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 0.581 3.323 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X4Y121 FDCE f u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.504 1.985 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.014 r u_core/bufg_ft601/O net (fo=310, routed) 0.936 2.950 u_core/gen_ft2232h.usb_inst/CLK SLICE_X4Y121 FDCE r u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[0]/C clock pessimism -0.380 2.569 SLICE_X4Y121 FDCE (Remov_fdce_C_CLR) -0.092 2.477 u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[0] ------------------------------------------------------------------- required time -2.477 arrival time 3.323 ------------------------------------------------------------------- slack 0.846