Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Thu Apr 16 19:12:52 2026 | Host : jason-pc running 64-bit Ubuntu 25.10 | Command : report_timing_summary -file /home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA/build_50t/reports_50t/02_timing_summary.rpt | Design : radar_system_top_50t | Device : 7a50t-ftg256 | Speed File : -2 PRODUCTION 1.23 2018-06-13 | Design State : Physopt postRoute ---------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (15) 6. checking no_output_delay (27) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (15) ------------------------------- There are 11 input ports with no input delay specified. (HIGH) There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (27) -------------------------------- There are 27 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.068 0.000 0 42872 0.046 0.000 0 42848 0.361 0.000 0 14994 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- adc_dco_p {0.000 1.250} 2.500 400.000 clk_mmcm_fb_out {0.000 1.250} 2.500 400.000 clk_mmcm_out0 {0.000 1.250} 2.500 400.000 clk_100m {0.000 5.000} 10.000 100.000 clk_120m_dac {0.000 4.167} 8.333 120.005 ft_clkout {0.000 8.334} 16.667 59.999 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- adc_dco_p 0.920 0.000 0 8 0.361 0.000 0 10 clk_mmcm_fb_out 0.908 0.000 0 3 clk_mmcm_out0 0.068 0.000 0 3155 0.104 0.000 0 3155 0.684 0.000 0 764 clk_100m 0.156 0.000 0 36484 0.046 0.000 0 36484 3.870 0.000 0 13851 clk_120m_dac 0.627 0.000 0 102 0.121 0.000 0 102 3.666 0.000 0 70 ft_clkout 9.887 0.000 0 525 0.117 0.000 0 525 7.833 0.000 0 296 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- adc_dco_p clk_mmcm_out0 0.205 0.000 0 16 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_100m clk_100m 1.537 0.000 0 1916 0.883 0.000 0 1916 **async_default** clk_120m_dac clk_120m_dac 0.735 0.000 0 45 1.423 0.000 0 45 **async_default** clk_mmcm_out0 clk_mmcm_out0 0.192 0.000 0 339 0.491 0.000 0 339 **async_default** ft_clkout ft_clkout 11.092 0.000 0 282 0.680 0.000 0 282 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: adc_dco_p Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: adc_d_p[4] (input port clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: adc_dco_p Path Type: Setup (Max at Fast Process Corner) Requirement: 1.250ns (adc_dco_p rise@2.500ns - adc_dco_p fall@1.250ns) Data Path Delay: 0.450ns (logic 0.450ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUFDS=1) Input Delay: 1.000ns Clock Path Skew: 1.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.167ns = ( 3.667 - 2.500 ) Source Clock Delay (SCD): 0.000ns = ( 1.250 - 1.250 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.043ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.050ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock adc_dco_p fall edge) 1.250 1.250 f input delay 1.000 2.250 R10 0.000 2.250 r adc_d_p[4] (IN) net (fo=0) 0.000 2.250 u_core/rx_inst/adc/adc_d_p[4] R10 IBUFDS (Prop_ibufds_I_O) 0.450 2.700 r u_core/rx_inst/adc/data_buffers[4].ibufds_data/O net (fo=1, routed) 0.000 2.700 u_core/rx_inst/adc/adc_data_4 ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D ------------------------------------------------------------------- ------------------- (clock adc_dco_p rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 2.913 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.179 3.092 u_core/rx_inst/adc/adc_dco BUFIO_X0Y2 BUFIO (Prop_bufio_I_O) 0.484 3.576 r u_core/rx_inst/adc/bufio_dco/O net (fo=8, routed) 0.091 3.667 u_core/rx_inst/adc/adc_dco_bufio ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C clock pessimism 0.000 3.667 clock uncertainty -0.043 3.624 ILOGIC_X0Y16 IDDR (Setup_iddr_C_D) -0.003 3.621 u_core/rx_inst/adc/iddr_gen[4].iddr_inst ------------------------------------------------------------------- required time 3.621 arrival time -2.700 ------------------------------------------------------------------- slack 0.920 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: adc_dco_p Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { adc_dco_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDDR/C n/a 1.474 2.500 1.026 ILOGIC_X0Y34 u_core/rx_inst/adc/iddr_gen[0].iddr_inst/C Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_fb_out To Clock: clk_mmcm_fb_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.908ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_fb_out Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 2.500 0.908 BUFGCTRL_X0Y2 u_core/rx_inst/adc/mmcm_inst/bufg_feedback/I Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.068ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.104ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.684ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.068ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_400m_reg_rep__2/C (rising edge-triggered cell FDPE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_i_inst/integrator_sampled_comb_reg[0]/R (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.916ns (logic 0.433ns (22.598%) route 1.483ns (77.402%)) Logic Levels: 0 Clock Path Skew: -0.111ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.987ns = ( 4.487 - 2.500 ) Source Clock Delay (SCD): 2.111ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 1.516 2.111 u_core/rx_inst/ddc/clk_400m SLICE_X30Y106 FDPE r u_core/rx_inst/ddc/reset_400m_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X30Y106 FDPE (Prop_fdpe_C_Q) 0.433 2.544 r u_core/rx_inst/ddc/reset_400m_reg_rep__2/Q net (fo=46, routed) 1.483 4.027 u_core/rx_inst/ddc/cic_i_inst/integrator_sampled_comb_reg[27]_0[0] SLICE_X57Y128 FDRE r u_core/rx_inst/ddc/cic_i_inst/integrator_sampled_comb_reg[0]/R ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 1.390 4.487 u_core/rx_inst/ddc/cic_i_inst/clk_400m SLICE_X57Y128 FDRE r u_core/rx_inst/ddc/cic_i_inst/integrator_sampled_comb_reg[0]/C clock pessimism 0.013 4.500 clock uncertainty -0.053 4.447 SLICE_X57Y128 FDRE (Setup_fdre_C_R) -0.352 4.095 u_core/rx_inst/ddc/cic_i_inst/integrator_sampled_comb_reg[0] ------------------------------------------------------------------- required time 4.095 arrival time -4.027 ------------------------------------------------------------------- slack 0.068 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.104ns (arrival time - required time) Source: u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__3/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/CEP (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.537ns (logic 0.141ns (26.236%) route 0.396ns (73.765%)) Logic Levels: 0 Clock Path Skew: 0.437ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.115ns Source Clock Delay (SCD): 0.865ns Clock Pessimism Removal (CPR): -0.187ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 0.561 0.865 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X33Y93 FDRE r u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__3/C ------------------------------------------------------------------- ------------------- SLICE_X33Y93 FDRE (Prop_fdre_C_Q) 0.141 1.006 r u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__3/Q net (fo=4, routed) 0.396 1.403 u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__3_n_0 DSP48_X0Y41 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/CEP ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 1.003 1.115 u_core/rx_inst/ddc/cic_q_inst/clk_400m DSP48_X0Y41 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/CLK clock pessimism 0.187 1.302 DSP48_X0Y41 DSP48E1 (Hold_dsp48e1_CLK_CEP) -0.004 1.298 u_core/rx_inst/ddc/cic_q_inst/comb_reg[1] ------------------------------------------------------------------- required time -1.298 arrival time 1.403 ------------------------------------------------------------------- slack 0.104 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_out0 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 1.816 2.500 0.684 DSP48_X0Y33 u_core/rx_inst/ddc/dsp_mixer_i/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 Low Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X36Y62 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X36Y62 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.156ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.046ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.156ns (required time - arrival time) Source: u_core/cfar_inst/r_guard_reg[0]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/cfar_inst/lagging_sum_reg[25]/D (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.907ns (logic 3.508ns (35.411%) route 6.399ns (64.589%)) Logic Levels: 17 (CARRY4=7 LUT2=2 LUT4=1 LUT5=1 LUT6=3 MUXF7=2 MUXF8=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.436ns = ( 14.436 - 10.000 ) Source Clock Delay (SCD): 4.546ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=13866, routed) 1.347 4.546 u_core/cfar_inst/clk_100m_buf SLICE_X39Y88 FDCE r u_core/cfar_inst/r_guard_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y88 FDCE (Prop_fdce_C_Q) 0.379 4.925 r u_core/cfar_inst/r_guard_reg[0]/Q net (fo=8, routed) 0.422 5.347 u_core/cfar_inst/r_guard[0] SLICE_X40Y88 LUT2 (Prop_lut2_I0_O) 0.105 5.452 r u_core/cfar_inst/lagging_count[9]_i_14/O net (fo=1, routed) 0.000 5.452 u_core/cfar_inst/lagging_count[9]_i_14_n_0 SLICE_X40Y88 CARRY4 (Prop_carry4_S[0]_O[1]) 0.343 5.795 r u_core/cfar_inst/lagging_count_reg[9]_i_10/O[1] net (fo=2176, routed) 2.017 7.812 u_core/cfar_inst/lagging_count_reg[9]_i_10_n_6 SLICE_X53Y58 LUT6 (Prop_lut6_I2_O) 0.250 8.062 r u_core/cfar_inst/lagging_sum[7]_i_468/O net (fo=1, routed) 0.000 8.062 u_core/cfar_inst/lagging_sum[7]_i_468_n_0 SLICE_X53Y58 MUXF7 (Prop_muxf7_I1_O) 0.206 8.268 r u_core/cfar_inst/lagging_sum_reg[7]_i_203/O net (fo=1, routed) 0.000 8.268 u_core/cfar_inst/lagging_sum_reg[7]_i_203_n_0 SLICE_X53Y58 MUXF8 (Prop_muxf8_I0_O) 0.085 8.353 r u_core/cfar_inst/lagging_sum_reg[7]_i_71/O net (fo=1, routed) 1.018 9.371 u_core/cfar_inst/lagging_sum_reg[7]_i_71_n_0 SLICE_X46Y64 LUT6 (Prop_lut6_I0_O) 0.264 9.635 r u_core/cfar_inst/lagging_sum[7]_i_36/O net (fo=1, routed) 0.000 9.635 u_core/cfar_inst/lagging_sum[7]_i_36_n_0 SLICE_X46Y64 MUXF7 (Prop_muxf7_I1_O) 0.178 9.813 r u_core/cfar_inst/lagging_sum_reg[7]_i_19/O net (fo=1, routed) 1.581 11.394 u_core/cfar_inst/lagging_sum_reg[7]_i_19_n_0 SLICE_X42Y99 LUT6 (Prop_lut6_I0_O) 0.241 11.635 r u_core/cfar_inst/lagging_sum[7]_i_15/O net (fo=1, routed) 0.345 11.981 u_core/cfar_inst/lagging_sum[7]_i_15_n_0 SLICE_X41Y101 LUT4 (Prop_lut4_I0_O) 0.105 12.086 r u_core/cfar_inst/lagging_sum[7]_i_11/O net (fo=2, routed) 0.235 12.320 u_core/cfar_inst/lagging_sum[7]_i_11_n_0 SLICE_X41Y102 LUT5 (Prop_lut5_I1_O) 0.105 12.425 r u_core/cfar_inst/lagging_sum[7]_i_3/O net (fo=2, routed) 0.375 12.800 u_core/cfar_inst/lagging_sum[7]_i_3_n_0 SLICE_X40Y103 CARRY4 (Prop_carry4_DI[3]_CO[3]) 0.318 13.118 r u_core/cfar_inst/lagging_sum_reg[7]_i_2/CO[3] net (fo=1, routed) 0.000 13.118 u_core/cfar_inst/lagging_sum_reg[7]_i_2_n_0 SLICE_X40Y104 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 13.216 r u_core/cfar_inst/lagging_sum_reg[11]_i_2/CO[3] net (fo=1, routed) 0.000 13.216 u_core/cfar_inst/lagging_sum_reg[11]_i_2_n_0 SLICE_X40Y105 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 13.314 r u_core/cfar_inst/lagging_sum_reg[15]_i_2/CO[3] net (fo=1, routed) 0.000 13.314 u_core/cfar_inst/lagging_sum_reg[15]_i_2_n_0 SLICE_X40Y106 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 13.412 r u_core/cfar_inst/lagging_sum_reg[19]_i_2/CO[3] net (fo=1, routed) 0.000 13.412 u_core/cfar_inst/lagging_sum_reg[19]_i_2_n_0 SLICE_X40Y107 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 13.510 r u_core/cfar_inst/lagging_sum_reg[23]_i_2/CO[3] net (fo=1, routed) 0.000 13.510 u_core/cfar_inst/lagging_sum_reg[23]_i_2_n_0 SLICE_X40Y108 CARRY4 (Prop_carry4_CI_O[1]) 0.265 13.775 r u_core/cfar_inst/lagging_sum_reg[25]_i_2/O[1] net (fo=1, routed) 0.405 14.181 u_core/cfar_inst/lagging_sum_reg[25]_i_2_n_6 SLICE_X41Y108 LUT2 (Prop_lut2_I1_O) 0.272 14.453 r u_core/cfar_inst/lagging_sum[25]_i_1/O net (fo=1, routed) 0.000 14.453 u_core/cfar_inst/lagging_sum[25]_i_1_n_0 SLICE_X41Y108 FDCE r u_core/cfar_inst/lagging_sum_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=13866, routed) 1.396 14.436 u_core/cfar_inst/clk_100m_buf SLICE_X41Y108 FDCE r u_core/cfar_inst/lagging_sum_reg[25]/C clock pessimism 0.165 14.601 clock uncertainty -0.061 14.539 SLICE_X41Y108 FDCE (Setup_fdce_C_D) 0.069 14.608 u_core/cfar_inst/lagging_sum_reg[25] ------------------------------------------------------------------- required time 14.608 arrival time -14.453 ------------------------------------------------------------------- slack 0.156 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.046ns (arrival time - required time) Source: u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][15]/C (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/ddc/fir_i_inst/add_l3_reg[1][15]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 0.444ns (logic 0.273ns (61.484%) route 0.171ns (38.516%)) Logic Levels: 2 (CARRY4=1 LUT2=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.000ns Source Clock Delay (SCD): 1.490ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=13866, routed) 0.569 1.490 u_core/rx_inst/ddc/fir_i_inst/clk_100m_buf SLICE_X10Y49 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][15]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y49 FDRE (Prop_fdre_C_Q) 0.164 1.654 r u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][15]/Q net (fo=2, routed) 0.171 1.825 u_core/rx_inst/ddc/fir_i_inst/add_l2_reg[2][31]_0[15] SLICE_X12Y50 LUT2 (Prop_lut2_I0_O) 0.045 1.870 r u_core/rx_inst/ddc/fir_i_inst/add_l3[1][15]_i_2/O net (fo=1, routed) 0.000 1.870 u_core/rx_inst_n_1013 SLICE_X12Y50 CARRY4 (Prop_carry4_S[3]_O[3]) 0.064 1.934 r u_core/ddc/fir_i_inst/add_l3_reg[1][15]_i_1/O[3] net (fo=1, routed) 0.000 1.934 u_core/rx_inst/ddc/fir_i_inst/add_l3_reg[1][31]_0[15] SLICE_X12Y50 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l3_reg[1][15]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=13866, routed) 0.833 2.000 u_core/rx_inst/ddc/fir_i_inst/clk_100m_buf SLICE_X12Y50 FDRE r u_core/rx_inst/ddc/fir_i_inst/add_l3_reg[1][15]/C clock pessimism -0.246 1.754 SLICE_X12Y50 FDRE (Hold_fdre_C_D) 0.134 1.888 u_core/rx_inst/ddc/fir_i_inst/add_l3_reg[1][15] ------------------------------------------------------------------- required time -1.888 arrival time 1.934 ------------------------------------------------------------------- slack 0.046 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100m Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100m } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.272 10.000 6.728 DSP48_X0Y0 u_core/rx_inst/ddc/fir_i_inst/mult_reg_reg[0]/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X30Y119 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X30Y119 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 0.627ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.627ns (required time - arrival time) Source: u_core/tx_inst/plfm_chirp_inst/current_state_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/CE (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 7.211ns (logic 3.271ns (45.363%) route 3.940ns (54.637%)) Logic Levels: 10 (CARRY4=7 LUT2=2 LUT5=1) Clock Path Skew: -0.266ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.353ns = ( 12.686 - 8.333 ) Source Clock Delay (SCD): 4.783ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.584 4.783 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X2Y139 FDCE r u_core/tx_inst/plfm_chirp_inst/current_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X2Y139 FDCE (Prop_fdce_C_Q) 0.433 5.216 r u_core/tx_inst/plfm_chirp_inst/current_state_reg[1]/Q net (fo=51, routed) 0.654 5.871 u_core/tx_inst/plfm_chirp_inst/state[1] SLICE_X1Y138 LUT2 (Prop_lut2_I0_O) 0.105 5.976 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_i_6/O net (fo=1, routed) 0.000 5.976 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_i_6_n_0 SLICE_X1Y138 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.457 6.433 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry/CO[3] net (fo=1, routed) 0.000 6.433 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_n_0 SLICE_X1Y139 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 6.531 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__0/CO[3] net (fo=1, routed) 0.000 6.531 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__0_n_0 SLICE_X1Y140 CARRY4 (Prop_carry4_CI_CO[3]) 0.098 6.629 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__1/CO[3] net (fo=1, routed) 0.000 6.629 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__1_n_0 SLICE_X1Y141 CARRY4 (Prop_carry4_CI_CO[0]) 0.216 6.845 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_4__2/CO[0] net (fo=2, routed) 0.412 7.257 u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_4__2_n_3 SLICE_X4Y140 CARRY4 (Prop_carry4_CYINIT_CO[2]) 0.695 7.952 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_1__2/CO[2] net (fo=6, routed) 0.383 8.334 u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_1__2_n_1 SLICE_X3Y140 LUT2 (Prop_lut2_I1_O) 0.261 8.595 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_2__2/O net (fo=1, routed) 0.000 8.595 u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_2__2_n_0 SLICE_X3Y140 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.457 9.052 r u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__0/CO[3] net (fo=1, routed) 0.000 9.052 u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__0_n_0 SLICE_X3Y141 CARRY4 (Prop_carry4_CI_CO[2]) 0.190 9.242 r u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__1/CO[2] net (fo=17, routed) 1.098 10.340 u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__1_n_1 SLICE_X0Y124 LUT5 (Prop_lut5_I4_O) 0.261 10.601 r u_core/tx_inst/plfm_chirp_inst/chirp_counter[5]_i_1/O net (fo=6, routed) 1.393 11.994 u_core/tx_inst/plfm_chirp_inst/chirp_counter[5]_i_1_n_0 SLICE_X0Y89 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.312 12.686 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X0Y89 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1]/C clock pessimism 0.165 12.850 clock uncertainty -0.061 12.789 SLICE_X0Y89 FDCE (Setup_fdce_C_CE) -0.168 12.621 u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[1] ------------------------------------------------------------------- required time 12.621 arrival time -11.994 ------------------------------------------------------------------- slack 0.627 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.116ns Source Clock Delay (SCD): 1.595ns Clock Pessimism Removal (CPR): 0.521ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.673 1.595 u_core/tx_inst/cdc_chirp_toggle/clk_120m_dac_buf SLICE_X1Y144 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X1Y144 FDRE (Prop_fdre_C_Q) 0.141 1.736 r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/Q net (fo=1, routed) 0.055 1.791 u_core/tx_inst/cdc_chirp_toggle/sync_chain[0] SLICE_X1Y144 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.948 2.116 u_core/tx_inst/cdc_chirp_toggle/clk_120m_dac_buf SLICE_X1Y144 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/C clock pessimism -0.521 1.595 SLICE_X1Y144 FDRE (Hold_fdre_C_D) 0.075 1.670 u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1] ------------------------------------------------------------------- required time -1.670 arrival time 1.791 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_120m_dac Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { clk_120m_dac } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.170 8.333 6.163 RAMB36_X0Y23 u_core/tx_inst/plfm_chirp_inst/long_chirp_rd_data_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X3Y144 u_core/chirp_frame_toggle_120m_reg/C High Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X3Y144 u_core/chirp_frame_toggle_120m_reg/C --------------------------------------------------------------------------------------------------- From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 9.887ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.117ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 9.887ns (required time - arrival time) Source: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/ft_data_out_reg[4]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 6.665ns (logic 1.147ns (17.209%) route 5.518ns (82.791%)) Logic Levels: 4 (LUT5=2 LUT6=2) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.947ns = ( 21.614 - 16.667 ) Source Clock Delay (SCD): 5.454ns Clock Pessimism Removal (CPR): 0.467ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.488 3.944 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.025 r u_core/bufg_ft601/O net (fo=295, routed) 1.429 5.454 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X61Y17 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X61Y17 FDCE (Prop_fdce_C_Q) 0.379 5.833 r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[1]/Q net (fo=64, routed) 2.556 8.389 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg_n_0_[1] SLICE_X50Y23 LUT6 (Prop_lut6_I2_O) 0.105 8.494 r u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_12/O net (fo=1, routed) 1.118 9.612 u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_12_n_0 SLICE_X62Y24 LUT5 (Prop_lut5_I3_O) 0.115 9.727 r u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_9/O net (fo=1, routed) 1.028 10.755 u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_9_n_0 SLICE_X63Y23 LUT5 (Prop_lut5_I4_O) 0.281 11.036 r u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_5/O net (fo=1, routed) 0.816 11.852 u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_5_n_0 SLICE_X61Y33 LUT6 (Prop_lut6_I5_O) 0.267 12.119 r u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_1/O net (fo=1, routed) 0.000 12.119 u_core/gen_ft2232h.usb_inst/ft_data_out[4]_i_1_n_0 SLICE_X61Y33 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[4]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.157 20.214 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.291 r u_core/bufg_ft601/O net (fo=295, routed) 1.324 21.614 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X61Y33 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[4]/C clock pessimism 0.467 22.082 clock uncertainty -0.106 21.976 SLICE_X61Y33 FDCE (Setup_fdce_C_D) 0.030 22.006 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[4] ------------------------------------------------------------------- required time 22.006 arrival time -12.119 ------------------------------------------------------------------- slack 9.887 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.117ns (arrival time - required time) Source: u_core/gen_ft2232h.usb_inst/rd_shift_reg_reg[11]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/cmd_value_reg[11]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.206ns (logic 0.141ns (68.437%) route 0.065ns (31.563%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.869ns Source Clock Delay (SCD): 2.229ns Clock Pessimism Removal (CPR): 0.627ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.322 1.614 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.640 r u_core/bufg_ft601/O net (fo=295, routed) 0.589 2.229 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X65Y32 FDCE r u_core/gen_ft2232h.usb_inst/rd_shift_reg_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y32 FDCE (Prop_fdce_C_Q) 0.141 2.370 r u_core/gen_ft2232h.usb_inst/rd_shift_reg_reg[11]/Q net (fo=2, routed) 0.065 2.435 u_core/gen_ft2232h.usb_inst/rd_shift_reg_reg_n_0_[11] SLICE_X64Y32 FDCE r u_core/gen_ft2232h.usb_inst/cmd_value_reg[11]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.502 1.983 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.012 r u_core/bufg_ft601/O net (fo=295, routed) 0.858 2.869 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X64Y32 FDCE r u_core/gen_ft2232h.usb_inst/cmd_value_reg[11]/C clock pessimism -0.627 2.242 SLICE_X64Y32 FDCE (Hold_fdce_C_D) 0.076 2.318 u_core/gen_ft2232h.usb_inst/cmd_value_reg[11] ------------------------------------------------------------------- required time -2.318 arrival time 2.435 ------------------------------------------------------------------- slack 0.117 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ft_clkout Waveform(ns): { 0.000 8.333 } Period(ns): 16.667 Sources: { ft_clkout } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.170 16.667 14.497 RAMB18_X2Y19 u_core/gen_ft2232h.usb_inst/detect_bram_reg_2/CLKBWRCLK Low Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X60Y33 u_core/cmd_valid_toggle_ft601_reg/C High Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X60Y33 u_core/cmd_valid_toggle_ft601_reg/C --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.205ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.205ns (required time - arrival time) Source: u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_fall_bufg_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (MaxDelay Path 2.500ns) Data Path Delay: 2.215ns (logic 0.448ns (20.227%) route 1.767ns (79.773%)) Logic Levels: 0 Timing Exception: MaxDelay Path 2.500ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- ILOGIC_X0Y2 0.000 0.000 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/C ILOGIC_X0Y2 IDDR (Prop_iddr_C_Q2) 0.448 0.448 r u_core/rx_inst/adc/iddr_gen[7].iddr_inst/Q2 net (fo=1, routed) 1.767 2.215 u_core/rx_inst/adc/adc_data_fall[7] SLICE_X12Y40 FDRE r u_core/rx_inst/adc/adc_data_fall_bufg_reg[7]/D ------------------------------------------------------------------- ------------------- max delay 2.500 2.500 SLICE_X12Y40 FDRE (Setup_fdre_C_D) -0.080 2.420 u_core/rx_inst/adc/adc_data_fall_bufg_reg[7] ------------------------------------------------------------------- required time 2.420 arrival time -2.215 ------------------------------------------------------------------- slack 0.205 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 1.537ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.883ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.537ns (required time - arrival time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/doppler_proc/fft_inst/in_buf_wdata_im_reg[9]/CLR (recovery check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 8.198ns (logic 0.588ns (7.173%) route 7.610ns (92.827%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.055ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.440ns = ( 14.440 - 10.000 ) Source Clock Delay (SCD): 4.550ns Clock Pessimism Removal (CPR): 0.165ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=13866, routed) 1.351 4.550 u_core/clk_100m_buf SLICE_X29Y57 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y57 FDCE (Prop_fdce_C_Q) 0.348 4.898 r u_core/reset_sync_reg[1]/Q net (fo=18, routed) 1.270 6.168 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X4Y29 LUT1 (Prop_lut1_I0_O) 0.240 6.408 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=5012, routed) 6.340 12.748 u_core/rx_inst/doppler_proc/fft_inst/bf_prod_re1__2_7 SLICE_X54Y145 FDCE f u_core/rx_inst/doppler_proc/fft_inst/in_buf_wdata_im_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=13866, routed) 1.400 14.440 u_core/rx_inst/doppler_proc/fft_inst/clk_100m_buf SLICE_X54Y145 FDCE r u_core/rx_inst/doppler_proc/fft_inst/in_buf_wdata_im_reg[9]/C clock pessimism 0.165 14.605 clock uncertainty -0.061 14.543 SLICE_X54Y145 FDCE (Recov_fdce_C_CLR) -0.258 14.285 u_core/rx_inst/doppler_proc/fft_inst/in_buf_wdata_im_reg[9] ------------------------------------------------------------------- required time 14.285 arrival time -12.748 ------------------------------------------------------------------- slack 1.537 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.883ns (arrival time - required time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/tx_inst/elevation_edge/signal_in_prev2_reg/CLR (removal check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 1.115ns (logic 0.226ns (20.268%) route 0.889ns (79.732%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.024ns Source Clock Delay (SCD): 1.479ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=13866, routed) 0.558 1.479 u_core/clk_100m_buf SLICE_X29Y57 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y57 FDCE (Prop_fdce_C_Q) 0.128 1.607 r u_core/reset_sync_reg[1]/Q net (fo=18, routed) 0.672 2.279 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X4Y29 LUT1 (Prop_lut1_I0_O) 0.098 2.377 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=5012, routed) 0.217 2.595 u_core/tx_inst/elevation_edge/RSTM SLICE_X2Y29 FDCE f u_core/tx_inst/elevation_edge/signal_in_prev2_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=13866, routed) 0.857 2.024 u_core/tx_inst/elevation_edge/clk_100m_buf SLICE_X2Y29 FDCE r u_core/tx_inst/elevation_edge/signal_in_prev2_reg/C clock pessimism -0.246 1.778 SLICE_X2Y29 FDCE (Remov_fdce_C_CLR) -0.067 1.711 u_core/tx_inst/elevation_edge/signal_in_prev2_reg ------------------------------------------------------------------- required time -1.711 arrival time 2.595 ------------------------------------------------------------------- slack 0.883 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 0.735ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.423ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.735ns (required time - arrival time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/chirp_frame_toggle_120m_reg/CLR (recovery check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 7.316ns (logic 0.590ns (8.064%) route 6.726ns (91.936%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.510ns = ( 12.843 - 8.333 ) Source Clock Delay (SCD): 4.559ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.360 4.559 u_core/clk_120m_dac_buf SLICE_X15Y27 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y27 FDCE (Prop_fdce_C_Q) 0.348 4.907 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.347 5.254 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X15Y27 LUT1 (Prop_lut1_I0_O) 0.242 5.496 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 6.379 11.875 u_core/tx_inst_n_11 SLICE_X3Y144 FDCE f u_core/chirp_frame_toggle_120m_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.470 12.843 u_core/clk_120m_dac_buf SLICE_X3Y144 FDCE r u_core/chirp_frame_toggle_120m_reg/C clock pessimism 0.159 13.002 clock uncertainty -0.061 12.941 SLICE_X3Y144 FDCE (Recov_fdce_C_CLR) -0.331 12.610 u_core/chirp_frame_toggle_120m_reg ------------------------------------------------------------------- required time 12.610 arrival time -11.875 ------------------------------------------------------------------- slack 0.735 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.423ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_reg/CLR (removal check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 1.408ns (logic 0.227ns (16.117%) route 1.181ns (83.883%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.077ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.036ns Source Clock Delay (SCD): 1.480ns Clock Pessimism Removal (CPR): 0.480ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.558 1.480 u_core/clk_120m_dac_buf SLICE_X15Y27 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y27 FDCE (Prop_fdce_C_Q) 0.128 1.608 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.142 1.750 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X15Y27 LUT1 (Prop_lut1_I0_O) 0.099 1.849 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 1.039 2.888 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X0Y48 FDCE f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.869 2.036 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X0Y48 FDCE r u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_reg/C clock pessimism -0.480 1.557 SLICE_X0Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.465 u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_reg ------------------------------------------------------------------- required time -1.465 arrival time 2.888 ------------------------------------------------------------------- slack 1.423 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.192ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.491ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.192ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[5]/PRE (recovery check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.977ns (logic 0.484ns (24.479%) route 1.493ns (75.521%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.014ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.904ns = ( 4.404 - 2.500 ) Source Clock Delay (SCD): 1.954ns Clock Pessimism Removal (CPR): 0.064ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 1.359 1.954 u_core/rx_inst/ddc/clk_400m SLICE_X57Y89 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y89 FDCE (Prop_fdce_C_Q) 0.379 2.333 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=22, routed) 0.384 2.717 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X56Y87 LUT1 (Prop_lut1_I0_O) 0.105 2.822 f u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=371, routed) 1.109 3.931 u_core/rx_inst/ddc/nco_core/p_0_in__0 SLICE_X60Y80 FDPE f u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[5]/PRE ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 1.307 4.404 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X60Y80 FDPE r u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[5]/C clock pessimism 0.064 4.468 clock uncertainty -0.053 4.415 SLICE_X60Y80 FDPE (Recov_fdpe_C_PRE) -0.292 4.123 u_core/rx_inst/ddc/nco_core/cos_abs_reg_reg[5] ------------------------------------------------------------------- required time 4.123 arrival time -3.931 ------------------------------------------------------------------- slack 0.192 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.491ns (arrival time - required time) Source: u_core/rx_inst/adc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/CLR (removal check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.669ns (logic 0.227ns (33.938%) route 0.442ns (66.062%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.270ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.938ns Source Clock Delay (SCD): 0.855ns Clock Pessimism Removal (CPR): -0.187ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 0.551 0.855 u_core/rx_inst/adc/clk_400m SLICE_X32Y77 FDCE r u_core/rx_inst/adc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y77 FDCE (Prop_fdce_C_Q) 0.128 0.983 r u_core/rx_inst/adc/reset_sync_400m_reg[1]/Q net (fo=1, routed) 0.111 1.095 u_core/rx_inst/adc/reset_sync_400m[1] SLICE_X35Y77 LUT1 (Prop_lut1_I0_O) 0.099 1.194 f u_core/rx_inst/adc/dco_phase_i_2/O net (fo=10, routed) 0.331 1.524 u_core/rx_inst/adc/dco_phase_i_2_n_0 SLICE_X36Y62 FDCE f u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=762, routed) 0.825 0.938 u_core/rx_inst/adc/clk_400m SLICE_X36Y62 FDCE r u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C clock pessimism 0.187 1.125 SLICE_X36Y62 FDCE (Remov_fdce_C_CLR) -0.092 1.033 u_core/rx_inst/adc/adc_data_400m_reg_reg[0] ------------------------------------------------------------------- required time -1.033 arrival time 1.524 ------------------------------------------------------------------- slack 0.491 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 11.092ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.680ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 11.092ns (required time - arrival time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_words_reg[0][0]/CLR (recovery check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 5.049ns (logic 0.587ns (11.627%) route 4.462ns (88.373%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.089ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.879ns = ( 21.546 - 16.667 ) Source Clock Delay (SCD): 5.376ns Clock Pessimism Removal (CPR): 0.407ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.488 3.944 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.025 r u_core/bufg_ft601/O net (fo=295, routed) 1.351 5.376 u_core/ft601_clk_buf SLICE_X29Y26 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y26 FDCE (Prop_fdce_C_Q) 0.348 5.724 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.736 6.459 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X34Y23 LUT1 (Prop_lut1_I0_O) 0.239 6.698 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=282, routed) 3.726 10.424 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X45Y36 FDCE f u_core/gen_ft2232h.usb_inst/status_words_reg[0][0]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.157 20.214 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.291 r u_core/bufg_ft601/O net (fo=295, routed) 1.256 21.546 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X45Y36 FDCE r u_core/gen_ft2232h.usb_inst/status_words_reg[0][0]/C clock pessimism 0.407 21.954 clock uncertainty -0.106 21.848 SLICE_X45Y36 FDCE (Recov_fdce_C_CLR) -0.331 21.517 u_core/gen_ft2232h.usb_inst/status_words_reg[0][0] ------------------------------------------------------------------- required time 21.517 arrival time -10.424 ------------------------------------------------------------------- slack 11.092 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.680ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_words_reg[4][21]/CLR (removal check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.878ns (logic 0.226ns (25.741%) route 0.652ns (74.259%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.265ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.832ns Source Clock Delay (SCD): 2.191ns Clock Pessimism Removal (CPR): 0.376ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.322 1.614 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.640 r u_core/bufg_ft601/O net (fo=295, routed) 0.551 2.191 u_core/ft601_clk_buf SLICE_X29Y26 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X29Y26 FDCE (Prop_fdce_C_Q) 0.128 2.319 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.333 2.651 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X34Y23 LUT1 (Prop_lut1_I0_O) 0.098 2.749 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=282, routed) 0.319 3.069 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X46Y22 FDCE f u_core/gen_ft2232h.usb_inst/status_words_reg[4][21]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.502 1.983 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.012 r u_core/bufg_ft601/O net (fo=295, routed) 0.821 2.832 u_core/gen_ft2232h.usb_inst/ft_clk SLICE_X46Y22 FDCE r u_core/gen_ft2232h.usb_inst/status_words_reg[4][21]/C clock pessimism -0.376 2.456 SLICE_X46Y22 FDCE (Remov_fdce_C_CLR) -0.067 2.389 u_core/gen_ft2232h.usb_inst/status_words_reg[4][21] ------------------------------------------------------------------- required time -2.389 arrival time 3.069 ------------------------------------------------------------------- slack 0.680