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• v1.0.0-ft2232h 765aa279ac

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  mirror released this 2026-04-07 20:37:05 +00:00 | 91 commits to main since this release

  📅 Originally published on GitHub: Tue, 07 Apr 2026 20:37:36 GMT
  🏷️ Git tag created: Tue, 07 Apr 2026 20:37:05 GMT

  AERIS-10 50T Production Bitstream — FT2232H USB 2.0

  Vivado Build 15 bitstream for the XC7A50T-FTG256 production board with FT2232HQ USB 2.0 (8-bit, 245 Synchronous FIFO) replacing the FT601 USB 3.0 (32-bit) interface.

  Timing

  Metric	Value
  WNS	+0.088 ns
  WHS	+0.059 ns
  WPWS	+0.361 ns
  Failing Endpoints	0
  All constraints met	Yes

  Utilization (xc7a50tftg256-2)

  Resource	Used	Available	Util%
  LUTs	10,060	32,600	30.9%
  Flip-Flops	12,670	65,200	19.4%
  BRAM	17.5	75	23.3%
  DSP48E1	112	120	93.3%
  IOB	79	170	46.5%

  What Changed (from FT601 baseline)

  • RTL: Parametric USB_MODE in radar_system_top.v — generate block selects FT601 (MODE=0, 200T) or FT2232H (MODE=1, 50T)
  • New module: usb_data_interface_ft2232h.v — 8-bit FIFO interface for Channel A
  • Wrapper: radar_system_top_50t.v instantiates top with .USB_MODE(1)
  • DDC fix: Retiming in DDC chain for 400 MHz timing closure
  • Constraints: xc7a50t_ftg256.xdc updated with FT2232H pin map (Bank 35, 3.3V)
  • Python host: FT601 support removed, FT2232HConnection is the only data interface
  • CI: GitHub Actions running 101 tests (58 Python + 20 MCU C + 23 FPGA iverilog)

  Assets

  • radar_system_top_50t.bit — Production bitstream (program via Vivado/xsdb)
  • 02_timing_summary.rpt — Post-route timing report
  • 04_utilization.rpt — Post-route utilization report

  Build Environment

  • Vivado 2025.2 (lin64)
  • Device: xc7a50tftg256-2 (speed grade -2, PRODUCTION)
  • Top module: radar_system_top_50t

  Downloads

  • 02_timing_summary.rpt
    103 KiB

    2026-04-19 11:27:44 +00:00
  • 04_utilization.rpt
    12 KiB

    2026-04-19 11:27:44 +00:00
  • radar_system_top_50t.bit
    2.1 MiB

    2026-04-19 11:27:45 +00:00
  • Source Code (ZIP)
  • Source Code (TAR.GZ)