Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025 | Date : Mon Apr 13 21:20:45 2026 | Host : jason-pc running 64-bit Ubuntu 25.10 | Command : report_timing_summary -file /home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA/build_50t/reports_50t/02_timing_summary.rpt | Design : radar_system_top_50t | Device : 7a50t-ftg256 | Speed File : -2 PRODUCTION 1.23 2018-06-13 | Design State : Physopt postRoute ---------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (0) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (0) 5. checking no_input_delay (15) 6. checking no_output_delay (27) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (0) ------------------------ There are 0 register/latch pins with no clock. 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (0) ------------------------------------------------ There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (15) ------------------------------- There are 11 input ports with no input delay specified. (HIGH) There are 4 input ports with no input delay but user has a false path constraint. (MEDIUM) 6. checking no_output_delay (27) -------------------------------- There are 27 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.080 0.000 0 37284 0.056 0.000 0 37260 0.361 0.000 0 13074 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- adc_dco_p {0.000 1.250} 2.500 400.000 clk_mmcm_fb_out {0.000 1.250} 2.500 400.000 clk_mmcm_out0 {0.000 1.250} 2.500 400.000 clk_100m {0.000 5.000} 10.000 100.000 clk_120m_dac {0.000 4.167} 8.333 120.005 ft_clkout {0.000 8.334} 16.667 59.999 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- adc_dco_p 0.920 0.000 0 8 0.361 0.000 0 10 clk_mmcm_fb_out 0.908 0.000 0 3 clk_mmcm_out0 0.080 0.000 0 3300 0.066 0.000 0 3300 0.684 0.000 0 800 clk_100m 0.358 0.000 0 31215 0.056 0.000 0 31215 3.870 0.000 0 11880 clk_120m_dac 2.101 0.000 0 102 0.121 0.000 0 102 3.666 0.000 0 70 ft_clkout 9.413 0.000 0 370 0.121 0.000 0 370 7.833 0.000 0 311 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- adc_dco_p clk_mmcm_out0 0.246 0.000 0 16 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk_100m clk_100m 2.639 0.000 0 1582 0.789 0.000 0 1582 **async_default** clk_120m_dac clk_120m_dac 5.826 0.000 0 45 0.593 0.000 0 45 **async_default** clk_mmcm_out0 clk_mmcm_out0 0.339 0.000 0 339 0.418 0.000 0 339 **async_default** ft_clkout ft_clkout 10.728 0.000 0 307 0.548 0.000 0 307 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: adc_dco_p Setup : 0 Failing Endpoints, Worst Slack 0.920ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.920ns (required time - arrival time) Source: adc_d_p[4] (input port clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: adc_dco_p Path Type: Setup (Max at Fast Process Corner) Requirement: 1.250ns (adc_dco_p rise@2.500ns - adc_dco_p fall@1.250ns) Data Path Delay: 0.450ns (logic 0.450ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 1 (IBUFDS=1) Input Delay: 1.000ns Clock Path Skew: 1.167ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.167ns = ( 3.667 - 2.500 ) Source Clock Delay (SCD): 0.000ns = ( 1.250 - 1.250 ) Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.043ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.050ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock adc_dco_p fall edge) 1.250 1.250 f input delay 1.000 2.250 R10 0.000 2.250 r adc_d_p[4] (IN) net (fo=0) 0.000 2.250 u_core/rx_inst/adc/adc_d_p[4] R10 IBUFDS (Prop_ibufds_I_O) 0.450 2.700 r u_core/rx_inst/adc/data_buffers[4].ibufds_data/O net (fo=1, routed) 0.000 2.700 u_core/rx_inst/adc/adc_data_4 ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/D ------------------------------------------------------------------- ------------------- (clock adc_dco_p rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 2.913 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.179 3.092 u_core/rx_inst/adc/adc_dco BUFIO_X0Y2 BUFIO (Prop_bufio_I_O) 0.484 3.576 r u_core/rx_inst/adc/bufio_dco/O net (fo=8, routed) 0.091 3.667 u_core/rx_inst/adc/adc_dco_bufio ILOGIC_X0Y16 IDDR r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C clock pessimism 0.000 3.667 clock uncertainty -0.043 3.624 ILOGIC_X0Y16 IDDR (Setup_iddr_C_D) -0.003 3.621 u_core/rx_inst/adc/iddr_gen[4].iddr_inst ------------------------------------------------------------------- required time 3.621 arrival time -2.700 ------------------------------------------------------------------- slack 0.920 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: adc_dco_p Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { adc_dco_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a IDDR/C n/a 1.474 2.500 1.026 ILOGIC_X0Y34 u_core/rx_inst/adc/iddr_gen[0].iddr_inst/C Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 0.889 1.250 0.361 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_fb_out To Clock: clk_mmcm_fb_out Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 0.908ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_fb_out Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 2.500 0.908 BUFGCTRL_X0Y2 u_core/rx_inst/adc/mmcm_inst/bufg_feedback/I Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 2.500 97.500 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKFBIN --------------------------------------------------------------------------------------------------- From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.080ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.066ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 0.684ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.080ns (required time - arrival time) Source: u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__4_psdsp_28/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/C[41] (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.993ns (logic 0.379ns (38.173%) route 0.614ns (61.827%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.128ns = ( 4.628 - 2.500 ) Source Clock Delay (SCD): 2.168ns Clock Pessimism Removal (CPR): 0.093ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.133 0.728 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.081 0.809 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 1.359 2.168 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X55Y89 FDRE r u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__4_psdsp_28/C ------------------------------------------------------------------- ------------------- SLICE_X55Y89 FDRE (Prop_fdre_C_Q) 0.379 2.547 r u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__4_psdsp_28/Q net (fo=21, routed) 0.614 3.161 u_core/rx_inst/ddc/cic_q_inst/data_valid_comb_0_out_reg_rep__4_psdsp_psdsp_n_27 DSP48_X1Y34 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/C[41] ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.126 3.223 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.300 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 1.328 4.628 u_core/rx_inst/ddc/cic_q_inst/clk_400m DSP48_X1Y34 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_reg[1]/CLK clock pessimism 0.093 4.721 clock uncertainty -0.053 4.668 DSP48_X1Y34 DSP48E1 (Setup_dsp48e1_CLK_C[41]) -1.427 3.241 u_core/rx_inst/ddc/cic_q_inst/comb_reg[1] ------------------------------------------------------------------- required time 3.241 arrival time -3.161 ------------------------------------------------------------------- slack 0.080 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.066ns (arrival time - required time) Source: u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][11]/C (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/cic_q_inst/comb_0_dsp/B[11] (rising edge-triggered cell DSP48E1 clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.498ns (logic 0.141ns (28.319%) route 0.357ns (71.681%)) Logic Levels: 0 Clock Path Skew: 0.349ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.104ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): -0.180ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.042 0.347 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.373 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 0.562 0.934 u_core/rx_inst/ddc/cic_q_inst/clk_400m SLICE_X39Y97 FDRE r u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][11]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y97 FDRE (Prop_fdre_C_Q) 0.141 1.075 r u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg[0][0][11]/Q net (fo=1, routed) 0.357 1.432 u_core/rx_inst/ddc/cic_q_inst/comb_delay_reg_n_0_[0][0][11] DSP48_X0Y39 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_0_dsp/B[11] ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.046 0.159 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.188 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 0.916 1.104 u_core/rx_inst/ddc/cic_q_inst/clk_400m DSP48_X0Y39 DSP48E1 r u_core/rx_inst/ddc/cic_q_inst/comb_0_dsp/CLK clock pessimism 0.180 1.284 DSP48_X0Y39 DSP48E1 (Hold_dsp48e1_CLK_B[11]) 0.082 1.366 u_core/rx_inst/ddc/cic_q_inst/comb_0_dsp ------------------------------------------------------------------- required time -1.366 arrival time 1.432 ------------------------------------------------------------------- slack 0.066 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_mmcm_out0 Waveform(ns): { 0.000 1.250 } Period(ns): 2.500 Sources: { u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 1.816 2.500 0.684 DSP48_X1Y33 u_core/rx_inst/ddc/dsp_mixer_i/CLK Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X0Y0 u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 Low Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X40Y68 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.500 1.250 0.750 SLICE_X40Y68 u_core/rx_inst/adc/adc_data_400m_reg_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 0.358ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.056ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.358ns (required time - arrival time) Source: u_core/rx_inst/mf_dual/input_buffer_i_reg/CLKBWRCLK (rising edge-triggered cell RAMB18E1 clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/mf_dual/overlap_cache_i_reg[42][10]/D (rising edge-triggered cell FDRE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 9.435ns (logic 2.125ns (22.522%) route 7.310ns (77.478%)) Logic Levels: 0 Clock Path Skew: -0.098ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.346ns = ( 14.346 - 10.000 ) Source Clock Delay (SCD): 4.603ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11895, routed) 1.404 4.603 u_core/rx_inst/mf_dual/clk_100m_buf RAMB18_X1Y12 RAMB18E1 r u_core/rx_inst/mf_dual/input_buffer_i_reg/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB18_X1Y12 RAMB18E1 (Prop_ramb18e1_CLKBWRCLK_DOBDO[10]) 2.125 6.728 r u_core/rx_inst/mf_dual/input_buffer_i_reg/DOBDO[10] net (fo=129, routed) 7.310 14.038 u_core/rx_inst/mf_dual/buf_rdata_i[10] SLICE_X58Y81 FDRE r u_core/rx_inst/mf_dual/overlap_cache_i_reg[42][10]/D ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11895, routed) 1.306 14.346 u_core/rx_inst/mf_dual/clk_100m_buf SLICE_X58Y81 FDRE r u_core/rx_inst/mf_dual/overlap_cache_i_reg[42][10]/C clock pessimism 0.159 14.505 clock uncertainty -0.061 14.444 SLICE_X58Y81 FDRE (Setup_fdre_C_D) -0.047 14.397 u_core/rx_inst/mf_dual/overlap_cache_i_reg[42][10] ------------------------------------------------------------------- required time 14.397 arrival time -14.038 ------------------------------------------------------------------- slack 0.358 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.056ns (arrival time - required time) Source: u_core/cfar_inst/mag_waddr_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/cfar_inst/mag_mem_reg/ADDRARDADDR[6] (rising edge-triggered cell RAMB36E1 clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_100m Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 0.293ns (logic 0.141ns (48.118%) route 0.152ns (51.882%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.125ns Source Clock Delay (SCD): 1.567ns Clock Pessimism Removal (CPR): 0.505ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11895, routed) 0.645 1.567 u_core/cfar_inst/clk_100m_buf SLICE_X9Y102 FDCE r u_core/cfar_inst/mag_waddr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X9Y102 FDCE (Prop_fdce_C_Q) 0.141 1.708 r u_core/cfar_inst/mag_waddr_reg[2]/Q net (fo=1, routed) 0.152 1.860 u_core/cfar_inst/mag_waddr[2] RAMB36_X0Y20 RAMB36E1 r u_core/cfar_inst/mag_mem_reg/ADDRARDADDR[6] ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11895, routed) 0.958 2.125 u_core/cfar_inst/clk_100m_buf RAMB36_X0Y20 RAMB36E1 r u_core/cfar_inst/mag_mem_reg/CLKARDCLK clock pessimism -0.505 1.621 RAMB36_X0Y20 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) 0.183 1.804 u_core/cfar_inst/mag_mem_reg ------------------------------------------------------------------- required time -1.804 arrival time 1.860 ------------------------------------------------------------------- slack 0.056 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_100m Waveform(ns): { 0.000 5.000 } Period(ns): 10.000 Sources: { clk_100m } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a DSP48E1/CLK n/a 3.272 10.000 6.728 DSP48_X1Y0 u_core/rx_inst/ddc/fir_i_inst/mult_reg_reg[0]/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X30Y117 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X30Y117 u_core/rx_inst/doppler_proc/fft_inst/in_buf_im_reg_0_15_0_5/RAMA/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 2.101ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.666ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.101ns (required time - arrival time) Source: u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[2]/CE (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 5.797ns (logic 3.042ns (52.476%) route 2.755ns (47.524%)) Logic Levels: 10 (CARRY4=7 LUT3=1 LUT5=1 LUT6=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.348ns = ( 12.681 - 8.333 ) Source Clock Delay (SCD): 4.615ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.416 4.615 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X3Y85 FDCE r u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y85 FDCE (Prop_fdce_C_Q) 0.379 4.994 r u_core/tx_inst/plfm_chirp_inst/current_state_reg[2]/Q net (fo=58, routed) 1.049 6.044 u_core/tx_inst/plfm_chirp_inst/state[2] SLICE_X2Y79 LUT3 (Prop_lut3_I2_O) 0.105 6.149 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_i_4/O net (fo=1, routed) 0.000 6.149 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_i_4_n_0 SLICE_X2Y79 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.314 6.463 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry/CO[3] net (fo=1, routed) 0.000 6.463 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry_n_0 SLICE_X2Y80 CARRY4 (Prop_carry4_CI_CO[3]) 0.100 6.563 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__0/CO[3] net (fo=1, routed) 0.000 6.563 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__0_n_0 SLICE_X2Y81 CARRY4 (Prop_carry4_CI_CO[3]) 0.100 6.663 r u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__1/CO[3] net (fo=1, routed) 0.000 6.663 u_core/tx_inst/plfm_chirp_inst/sample_counter2_carry__1_n_0 SLICE_X2Y82 CARRY4 (Prop_carry4_CI_CO[0]) 0.207 6.870 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_4__12/CO[0] net (fo=2, routed) 0.266 7.136 u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_4__12_n_3 SLICE_X2Y83 CARRY4 (Prop_carry4_CYINIT_O[1]) 0.698 7.834 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_1__15/O[1] net (fo=1, routed) 0.426 8.259 u_core/tx_inst/plfm_chirp_inst/sample_counter2[14] SLICE_X3Y82 LUT6 (Prop_lut6_I0_O) 0.245 8.504 r u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_3__12/O net (fo=1, routed) 0.000 8.504 u_core/tx_inst/plfm_chirp_inst/i__carry__0_i_3__12_n_0 SLICE_X3Y82 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.440 8.944 r u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__0/CO[3] net (fo=1, routed) 0.000 8.944 u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__0_n_0 SLICE_X3Y83 CARRY4 (Prop_carry4_CI_CO[2]) 0.190 9.134 r u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__1/CO[2] net (fo=17, routed) 0.508 9.642 u_core/tx_inst/plfm_chirp_inst/sample_counter1_inferred__0/i__carry__1_n_1 SLICE_X5Y80 LUT5 (Prop_lut5_I4_O) 0.264 9.906 r u_core/tx_inst/plfm_chirp_inst/chirp_counter[5]_i_1/O net (fo=6, routed) 0.506 10.412 u_core/tx_inst/plfm_chirp_inst/chirp_counter[5]_i_1_n_0 SLICE_X7Y84 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.307 12.681 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X7Y84 FDCE r u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[2]/C clock pessimism 0.224 12.904 clock uncertainty -0.061 12.843 SLICE_X7Y84 FDCE (Setup_fdce_C_CE) -0.330 12.513 u_core/tx_inst/plfm_chirp_inst/chirp_counter_reg[2] ------------------------------------------------------------------- required time 12.513 arrival time -10.412 ------------------------------------------------------------------- slack 2.101 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/D (rising edge-triggered cell FDRE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: clk_120m_dac Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.018ns Source Clock Delay (SCD): 1.504ns Clock Pessimism Removal (CPR): 0.514ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.582 1.504 u_core/tx_inst/cdc_chirp_toggle/clk_120m_dac_buf SLICE_X3Y79 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X3Y79 FDRE (Prop_fdre_C_Q) 0.141 1.645 r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[0]/Q net (fo=1, routed) 0.055 1.700 u_core/tx_inst/cdc_chirp_toggle/sync_chain[0] SLICE_X3Y79 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.850 2.018 u_core/tx_inst/cdc_chirp_toggle/clk_120m_dac_buf SLICE_X3Y79 FDRE r u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1]/C clock pessimism -0.514 1.504 SLICE_X3Y79 FDRE (Hold_fdre_C_D) 0.075 1.579 u_core/tx_inst/cdc_chirp_toggle/sync_chain_reg[1] ------------------------------------------------------------------- required time -1.579 arrival time 1.700 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_120m_dac Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { clk_120m_dac } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 2.170 8.333 6.163 RAMB36_X0Y17 u_core/tx_inst/plfm_chirp_inst/long_chirp_rd_data_reg/CLKARDCLK Low Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X4Y79 u_core/chirp_frame_toggle_120m_reg/C High Pulse Width Slow FDCE/C n/a 0.500 4.167 3.666 SLICE_X4Y79 u_core/chirp_frame_toggle_120m_reg/C --------------------------------------------------------------------------------------------------- From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 9.413ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.833ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 9.413ns (required time - arrival time) Source: u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Setup (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 7.106ns (logic 1.017ns (14.313%) route 6.089ns (85.687%)) Logic Levels: 3 (LUT6=2 MUXF7=1) Clock Path Skew: -0.114ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.923ns = ( 21.590 - 16.667 ) Source Clock Delay (SCD): 5.518ns Clock Pessimism Removal (CPR): 0.481ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=310, routed) 1.425 5.518 u_core/gen_ft2232h.usb_inst/CLK SLICE_X60Y94 FDCE r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y94 FDCE (Prop_fdce_C_Q) 0.433 5.951 r u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg[2]/Q net (fo=51, routed) 3.812 9.763 u_core/gen_ft2232h.usb_inst/wr_byte_idx_reg_n_0_[2] SLICE_X20Y102 MUXF7 (Prop_muxf7_S_O) 0.227 9.990 r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6]_i_5/O net (fo=1, routed) 0.920 10.909 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6]_i_5_n_0 SLICE_X27Y100 LUT6 (Prop_lut6_I5_O) 0.252 11.161 r u_core/gen_ft2232h.usb_inst/ft_data_out[6]_i_2/O net (fo=1, routed) 1.357 12.519 u_core/gen_ft2232h.usb_inst/ft_data_out[6]_i_2_n_0 SLICE_X42Y97 LUT6 (Prop_lut6_I0_O) 0.105 12.623 r u_core/gen_ft2232h.usb_inst/ft_data_out[6]_i_1/O net (fo=1, routed) 0.000 12.623 u_core/gen_ft2232h.usb_inst/ft_data_out0_in[6] SLICE_X42Y97 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=310, routed) 1.245 21.590 u_core/gen_ft2232h.usb_inst/CLK SLICE_X42Y97 FDCE r u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6]/C clock pessimism 0.481 22.071 clock uncertainty -0.106 21.965 SLICE_X42Y97 FDCE (Setup_fdce_C_D) 0.072 22.037 u_core/gen_ft2232h.usb_inst/ft_data_out_reg[6] ------------------------------------------------------------------- required time 22.037 arrival time -12.623 ------------------------------------------------------------------- slack 9.413 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.121ns (arrival time - required time) Source: u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/D (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: ft_clkout Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.953ns Source Clock Delay (SCD): 2.305ns Clock Pessimism Removal (CPR): 0.648ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=310, routed) 0.647 2.305 u_core/gen_ft2232h.usb_inst/CLK SLICE_X19Y102 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X19Y102 FDCE (Prop_fdce_C_Q) 0.141 2.446 r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[0]/Q net (fo=1, routed) 0.055 2.501 u_core/gen_ft2232h.usb_inst/doppler_toggle_sync[0] SLICE_X19Y102 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=310, routed) 0.920 2.953 u_core/gen_ft2232h.usb_inst/CLK SLICE_X19Y102 FDCE r u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1]/C clock pessimism -0.648 2.305 SLICE_X19Y102 FDCE (Hold_fdce_C_D) 0.075 2.380 u_core/gen_ft2232h.usb_inst/doppler_toggle_sync_reg[1] ------------------------------------------------------------------- required time -2.380 arrival time 2.501 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ft_clkout Waveform(ns): { 0.000 8.333 } Period(ns): 16.667 Sources: { ft_clkout } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.592 16.667 15.075 BUFGCTRL_X0Y1 u_core/bufg_ft601/I Low Pulse Width Slow FDCE/C n/a 0.500 8.334 7.834 SLICE_X61Y92 u_core/cmd_valid_toggle_ft601_reg/C High Pulse Width Slow FDCE/C n/a 0.500 8.333 7.833 SLICE_X61Y92 u_core/cmd_valid_toggle_ft601_reg/C --------------------------------------------------------------------------------------------------- From Clock: adc_dco_p To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.246ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.246ns (required time - arrival time) Source: u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C (rising edge-triggered cell IDDR clocked by adc_dco_p {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/adc/adc_data_fall_bufg_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: clk_mmcm_out0 Path Type: Setup (Max at Slow Process Corner) Requirement: 2.500ns (MaxDelay Path 2.500ns) Data Path Delay: 2.166ns (logic 0.448ns (20.679%) route 1.718ns (79.321%)) Logic Levels: 0 Timing Exception: MaxDelay Path 2.500ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- ILOGIC_X0Y16 0.000 0.000 r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/C ILOGIC_X0Y16 IDDR (Prop_iddr_C_Q2) 0.448 0.448 r u_core/rx_inst/adc/iddr_gen[4].iddr_inst/Q2 net (fo=1, routed) 1.718 2.166 u_core/rx_inst/adc/adc_data_fall[4] SLICE_X13Y43 FDRE r u_core/rx_inst/adc/adc_data_fall_bufg_reg[4]/D ------------------------------------------------------------------- ------------------- max delay 2.500 2.500 SLICE_X13Y43 FDRE (Setup_fdre_C_D) -0.088 2.412 u_core/rx_inst/adc/adc_data_fall_bufg_reg[4] ------------------------------------------------------------------- required time 2.412 arrival time -2.166 ------------------------------------------------------------------- slack 0.246 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_100m To Clock: clk_100m Setup : 0 Failing Endpoints, Worst Slack 2.639ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.789ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.639ns (required time - arrival time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/rx_inst/mf_dual/buffer_read_ptr_reg[6]_rep/CLR (recovery check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 10.000ns (clk_100m rise@10.000ns - clk_100m rise@0.000ns) Data Path Delay: 6.891ns (logic 0.590ns (8.561%) route 6.301ns (91.438%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.078ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.303ns = ( 14.303 - 10.000 ) Source Clock Delay (SCD): 4.539ns Clock Pessimism Removal (CPR): 0.159ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_100m/O net (fo=11895, routed) 1.340 4.539 u_core/clk_100m_buf SLICE_X32Y81 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y81 FDCE (Prop_fdce_C_Q) 0.348 4.887 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 1.002 5.889 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X31Y97 LUT1 (Prop_lut1_I0_O) 0.242 6.131 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4576, routed) 5.299 11.430 u_core/rx_inst/mf_dual/bc_reg_reg SLICE_X57Y12 FDCE f u_core/rx_inst/mf_dual/buffer_read_ptr_reg[6]_rep/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 10.000 10.000 r E12 0.000 10.000 r clk_100m (IN) net (fo=0) 0.000 10.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 1.359 11.359 r clk_100m_IBUF_inst/O net (fo=1, routed) 1.604 12.963 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.077 13.040 r u_core/bufg_100m/O net (fo=11895, routed) 1.263 14.303 u_core/rx_inst/mf_dual/clk_100m_buf SLICE_X57Y12 FDCE r u_core/rx_inst/mf_dual/buffer_read_ptr_reg[6]_rep/C clock pessimism 0.159 14.462 clock uncertainty -0.061 14.400 SLICE_X57Y12 FDCE (Recov_fdce_C_CLR) -0.331 14.069 u_core/rx_inst/mf_dual/buffer_read_ptr_reg[6]_rep ------------------------------------------------------------------- required time 14.069 arrival time -11.430 ------------------------------------------------------------------- slack 2.639 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.789ns (arrival time - required time) Source: u_core/reset_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: u_core/host_self_test_trigger_reg/CLR (removal check against rising-edge clock clk_100m {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_100m rise@0.000ns - clk_100m rise@0.000ns) Data Path Delay: 1.080ns (logic 0.227ns (21.020%) route 0.853ns (78.980%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.358ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.082ns Source Clock Delay (SCD): 1.473ns Clock Pessimism Removal (CPR): 0.251ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_100m/O net (fo=11895, routed) 0.552 1.473 u_core/clk_100m_buf SLICE_X32Y81 FDCE r u_core/reset_sync_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X32Y81 FDCE (Prop_fdce_C_Q) 0.128 1.601 r u_core/reset_sync_reg[1]/Q net (fo=22, routed) 0.472 2.074 u_core/rx_inst/ddc/fir_q_inst/out[0] SLICE_X31Y97 LUT1 (Prop_lut1_I0_O) 0.099 2.173 f u_core/rx_inst/ddc/fir_q_inst/dst_data_reg[5]_i_1/O net (fo=4576, routed) 0.381 2.553 u_core/adc/mmcm_inst/RST0 SLICE_X34Y101 FDCE f u_core/host_self_test_trigger_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk_100m rise edge) 0.000 0.000 r E12 0.000 0.000 r clk_100m (IN) net (fo=0) 0.000 0.000 clk_100m E12 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_100m_IBUF_inst/O net (fo=1, routed) 0.689 1.138 u_core/clk_100m BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 1.167 r u_core/bufg_100m/O net (fo=11895, routed) 0.915 2.082 u_core/clk_100m_buf SLICE_X34Y101 FDCE r u_core/host_self_test_trigger_reg/C clock pessimism -0.251 1.832 SLICE_X34Y101 FDCE (Remov_fdce_C_CLR) -0.067 1.765 u_core/host_self_test_trigger_reg ------------------------------------------------------------------- required time -1.765 arrival time 2.553 ------------------------------------------------------------------- slack 0.789 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_120m_dac To Clock: clk_120m_dac Setup : 0 Failing Endpoints, Worst Slack 5.826ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.593ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.826ns (required time - arrival time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[0]/CLR (recovery check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.333ns (clk_120m_dac rise@8.333ns - clk_120m_dac rise@0.000ns) Data Path Delay: 2.146ns (logic 0.630ns (29.358%) route 1.516ns (70.642%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.031ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.350ns = ( 12.683 - 8.333 ) Source Clock Delay (SCD): 4.542ns Clock Pessimism Removal (CPR): 0.224ns Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.100ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.425 1.425 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.693 3.118 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.199 r u_core/bufg_120m/O net (fo=69, routed) 1.343 4.542 u_core/clk_120m_dac_buf SLICE_X8Y79 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y79 FDCE (Prop_fdce_C_Q) 0.398 4.940 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.124 5.065 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X8Y79 LUT1 (Prop_lut1_I0_O) 0.232 5.297 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 1.392 6.688 u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[7]_0 SLICE_X4Y86 FDCE f u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 8.333 8.333 r D13 0.000 8.333 r clk_120m_dac (IN) net (fo=0) 0.000 8.333 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 1.359 9.692 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 1.604 11.296 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 11.373 r u_core/bufg_120m/O net (fo=69, routed) 1.309 12.683 u_core/tx_inst/dac_interface_inst/clk_120m_dac_buf SLICE_X4Y86 FDCE r u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[0]/C clock pessimism 0.224 12.906 clock uncertainty -0.061 12.845 SLICE_X4Y86 FDCE (Recov_fdce_C_CLR) -0.331 12.514 u_core/tx_inst/dac_interface_inst/dac_data_reg_reg[0] ------------------------------------------------------------------- required time 12.514 arrival time -6.688 ------------------------------------------------------------------- slack 5.826 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.593ns (arrival time - required time) Source: u_core/reset_sync_120m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/CLR (removal check against rising-edge clock clk_120m_dac {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_120m_dac rise@0.000ns - clk_120m_dac rise@0.000ns) Data Path Delay: 0.588ns (logic 0.246ns (41.804%) route 0.342ns (58.196%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.016ns Source Clock Delay (SCD): 1.475ns Clock Pessimism Removal (CPR): 0.479ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.262 0.262 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.634 0.896 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.922 r u_core/bufg_120m/O net (fo=69, routed) 0.553 1.475 u_core/clk_120m_dac_buf SLICE_X8Y79 FDCE r u_core/reset_sync_120m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y79 FDCE (Prop_fdce_C_Q) 0.148 1.623 r u_core/reset_sync_120m_reg[1]/Q net (fo=1, routed) 0.055 1.678 u_core/tx_inst/plfm_chirp_inst/out[0] SLICE_X8Y79 LUT1 (Prop_lut1_I0_O) 0.098 1.776 f u_core/tx_inst/plfm_chirp_inst/rf_switch_ctrl_i_1/O net (fo=69, routed) 0.287 2.063 u_core/tx_inst/plfm_chirp_inst/reset_sync_120m_reg[1] SLICE_X6Y79 FDCE f u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk_120m_dac rise edge) 0.000 0.000 r D13 0.000 0.000 r clk_120m_dac (IN) net (fo=0) 0.000 0.000 clk_120m_dac D13 IBUF (Prop_ibuf_I_O) 0.450 0.450 r clk_120m_dac_IBUF_inst/O net (fo=1, routed) 0.689 1.139 u_core/clk_120m_dac BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.168 r u_core/bufg_120m/O net (fo=69, routed) 0.849 2.016 u_core/tx_inst/plfm_chirp_inst/clk_120m_dac_buf SLICE_X6Y79 FDCE r u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1]/C clock pessimism -0.479 1.537 SLICE_X6Y79 FDCE (Remov_fdce_C_CLR) -0.067 1.470 u_core/tx_inst/plfm_chirp_inst/sample_counter_reg[1] ------------------------------------------------------------------- required time -1.470 arrival time 2.063 ------------------------------------------------------------------- slack 0.593 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_mmcm_out0 To Clock: clk_mmcm_out0 Setup : 0 Failing Endpoints, Worst Slack 0.339ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.418ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.339ns (required time - arrival time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/nco_core/phase_accum_reg_reg[17]/CLR (recovery check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 2.500ns (clk_mmcm_out0 rise@2.500ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 1.873ns (logic 0.484ns (25.839%) route 1.389ns (74.161%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.049ns = ( 4.549 - 2.500 ) Source Clock Delay (SCD): 1.951ns Clock Pessimism Removal (CPR): -0.002ns Clock Uncertainty: 0.053ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.079ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.918 0.918 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.065 1.983 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.893 -0.911 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.425 0.514 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.081 0.595 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 1.356 1.951 u_core/rx_inst/ddc/bufg_clk400m_0_repN_alias SLICE_X45Y94 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y94 FDCE (Prop_fdce_C_Q) 0.379 2.330 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=5, routed) 0.251 2.581 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X45Y94 LUT1 (Prop_lut1_I0_O) 0.105 2.686 f u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=745, routed) 1.138 3.824 u_core/rx_inst/ddc/nco_core/p_0_in__0 SLICE_X49Y93 FDCE f u_core/rx_inst/ddc/nco_core/phase_accum_reg_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 2.500 2.500 r N14 0.000 2.500 r adc_dco_p (IN) net (fo=0) 0.000 2.500 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.877 3.377 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 1.004 4.381 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.718 1.663 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 1.357 3.020 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.077 3.097 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.126 3.223 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 3.300 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 1.249 4.549 u_core/rx_inst/ddc/nco_core/clk_400m SLICE_X49Y93 FDCE r u_core/rx_inst/ddc/nco_core/phase_accum_reg_reg[17]/C clock pessimism -0.002 4.547 clock uncertainty -0.053 4.494 SLICE_X49Y93 FDCE (Recov_fdce_C_CLR) -0.331 4.163 u_core/rx_inst/ddc/nco_core/phase_accum_reg_reg[17] ------------------------------------------------------------------- required time 4.163 arrival time -3.824 ------------------------------------------------------------------- slack 0.339 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.418ns (arrival time - required time) Source: u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C (rising edge-triggered cell FDCE clocked by clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Destination: u_core/rx_inst/ddc/mult_i_retimed_reg[2]/CLR (removal check against rising-edge clock clk_mmcm_out0 {rise@0.000ns fall@1.250ns period=2.500ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_mmcm_out0 rise@0.000ns - clk_mmcm_out0 rise@0.000ns) Data Path Delay: 0.695ns (logic 0.186ns (26.776%) route 0.509ns (73.224%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.344ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.018ns Source Clock Delay (SCD): 0.866ns Clock Pessimism Removal (CPR): -0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.413 0.413 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.440 0.853 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.063 -0.210 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.489 0.279 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.026 0.305 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.562 0.866 u_core/rx_inst/ddc/bufg_clk400m_0_repN_alias SLICE_X45Y94 FDCE r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X45Y94 FDCE (Prop_fdce_C_Q) 0.141 1.007 r u_core/rx_inst/ddc/reset_sync_400m_reg[1]/Q net (fo=5, routed) 0.130 1.138 u_core/rx_inst/ddc/nco_core/out[0] SLICE_X45Y94 LUT1 (Prop_lut1_I0_O) 0.045 1.183 f u_core/rx_inst/ddc/nco_core/reset_n_400m_inst/O net (fo=745, routed) 0.378 1.561 u_core/rx_inst/ddc/p_0_in__0_3 SLICE_X42Y93 FDCE f u_core/rx_inst/ddc/mult_i_retimed_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_mmcm_out0 rise edge) 0.000 0.000 r N14 0.000 0.000 r adc_dco_p (IN) net (fo=0) 0.000 0.000 u_core/rx_inst/adc/adc_dco_p N14 IBUFDS (Prop_ibufds_I_O) 0.448 0.448 r u_core/rx_inst/adc/ibufds_dco/O net (fo=2, routed) 0.480 0.928 u_core/rx_inst/adc/mmcm_inst/adc_dco MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.378 -0.450 r u_core/rx_inst/adc/mmcm_inst/mmcm_adc_400m/CLKOUT0 net (fo=1, routed) 0.534 0.084 u_core/rx_inst/adc/mmcm_inst/clk_mmcm_out0 BUFGCTRL_X0Y15 BUFG (Prop_bufg_I_O) 0.029 0.113 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_replica/O net (fo=3, routed) 0.046 0.159 u_core/rx_inst/adc/mmcm_inst/bufg_clk400m_0_repN BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.188 r u_core/rx_inst/adc/mmcm_inst/bufg_clk400m/O net (fo=795, routed) 0.831 1.018 u_core/rx_inst/ddc/clk_400m SLICE_X42Y93 FDCE r u_core/rx_inst/ddc/mult_i_retimed_reg[2]/C clock pessimism 0.192 1.210 SLICE_X42Y93 FDCE (Remov_fdce_C_CLR) -0.067 1.143 u_core/rx_inst/ddc/mult_i_retimed_reg[2] ------------------------------------------------------------------- required time -1.143 arrival time 1.561 ------------------------------------------------------------------- slack 0.418 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: ft_clkout To Clock: ft_clkout Setup : 0 Failing Endpoints, Worst Slack 10.728ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.548ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.728ns (required time - arrival time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/status_words_reg[4][15]/CLR (recovery check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 16.667ns (ft_clkout rise@16.667ns - ft_clkout rise@0.000ns) Data Path Delay: 5.480ns (logic 0.587ns (10.712%) route 4.893ns (89.288%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.095ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.924ns = ( 21.591 - 16.667 ) Source Clock Delay (SCD): 5.441ns Clock Pessimism Removal (CPR): 0.421ns Clock Uncertainty: 0.106ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.200ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.456 1.456 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.556 4.012 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.081 4.093 r u_core/bufg_ft601/O net (fo=310, routed) 1.348 5.441 u_core/ft601_clk_buf SLICE_X15Y81 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y81 FDCE (Prop_fdce_C_Q) 0.348 5.789 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.350 6.139 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X15Y84 LUT1 (Prop_lut1_I0_O) 0.239 6.378 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 4.543 10.921 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X50Y87 FDCE f u_core/gen_ft2232h.usb_inst/status_words_reg[4][15]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 16.667 16.667 r C4 0.000 16.667 r ft_clkout (IN) net (fo=0) 0.000 16.667 ft_clkout C4 IBUF (Prop_ibuf_I_O) 1.389 18.056 r ft_clkout_IBUF_inst/O net (fo=1, routed) 2.212 20.268 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.077 20.345 r u_core/bufg_ft601/O net (fo=310, routed) 1.246 21.591 u_core/gen_ft2232h.usb_inst/CLK SLICE_X50Y87 FDCE r u_core/gen_ft2232h.usb_inst/status_words_reg[4][15]/C clock pessimism 0.421 22.013 clock uncertainty -0.106 21.907 SLICE_X50Y87 FDCE (Recov_fdce_C_CLR) -0.258 21.649 u_core/gen_ft2232h.usb_inst/status_words_reg[4][15] ------------------------------------------------------------------- required time 21.649 arrival time -10.921 ------------------------------------------------------------------- slack 10.728 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.548ns (arrival time - required time) Source: u_core/reset_sync_ft601_reg[2]/C (rising edge-triggered cell FDCE clocked by ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Destination: u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[15]/CLR (removal check against rising-edge clock ft_clkout {rise@0.000ns fall@8.333ns period=16.667ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (ft_clkout rise@0.000ns - ft_clkout rise@0.000ns) Data Path Delay: 0.812ns (logic 0.226ns (27.819%) route 0.586ns (72.181%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.356ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.951ns Source Clock Delay (SCD): 2.215ns Clock Pessimism Removal (CPR): 0.380ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.292 0.292 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.340 1.632 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 1.658 r u_core/bufg_ft601/O net (fo=310, routed) 0.557 2.215 u_core/ft601_clk_buf SLICE_X15Y81 FDCE r u_core/reset_sync_ft601_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X15Y81 FDCE (Prop_fdce_C_Q) 0.128 2.343 r u_core/reset_sync_ft601_reg[2]/Q net (fo=1, routed) 0.165 2.508 u_core/gen_ft2232h.usb_inst/ft_rd_n_reg_0[0] SLICE_X15Y84 LUT1 (Prop_lut1_I0_O) 0.098 2.606 f u_core/gen_ft2232h.usb_inst/ft_rd_n_i_3/O net (fo=307, routed) 0.421 3.027 u_core/gen_ft2232h.usb_inst/reset_sync_ft601_reg[2] SLICE_X29Y100 FDCE f u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[15]/CLR ------------------------------------------------------------------- ------------------- (clock ft_clkout rise edge) 0.000 0.000 r C4 0.000 0.000 r ft_clkout (IN) net (fo=0) 0.000 0.000 ft_clkout C4 IBUF (Prop_ibuf_I_O) 0.480 0.480 r ft_clkout_IBUF_inst/O net (fo=1, routed) 1.524 2.004 u_core/ft601_clk_in BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.029 2.033 r u_core/bufg_ft601/O net (fo=310, routed) 0.918 2.951 u_core/gen_ft2232h.usb_inst/CLK SLICE_X29Y100 FDCE r u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[15]/C clock pessimism -0.380 2.571 SLICE_X29Y100 FDCE (Remov_fdce_C_CLR) -0.092 2.479 u_core/gen_ft2232h.usb_inst/doppler_imag_cap_reg[15] ------------------------------------------------------------------- required time -2.479 arrival time 3.027 ------------------------------------------------------------------- slack 0.548