ci: add GitHub Actions workflow for full regression suite

Three parallel jobs covering all AERIS-10 test infrastructure: - Python dashboard tests (58): protocol, connection, replay, opcodes, e2e - MCU firmware tests (20): bug regression (15) + Gap-3 safety (5) - FPGA regression (23 TBs + lint): unit, integration, and system e2e Triggers on push/PR to main and develop branches.
fix: remove server credentials from constraints README
2026-04-19 11:36:01 +00:00 · 2026-04-07 23:09:12 +03:00 · 2026-04-07 21:37:24 +03:00 · 2026-04-07 21:34:31 +03:00 · 2026-04-07 21:25:58 +03:00 · 2026-04-07 21:15:36 +03:00
173 changed files with 51942 additions and 1453980 deletions
@@ -1,21 +0,0 @@
-# Enforce LF line endings for all text files going forward.
-# Existing CRLF files are left as-is to avoid polluting git blame.
-* text=auto eol=lf
-
-# Binary files — ensure git doesn't mangle these
-*.npy binary
-*.h5 binary
-*.hdf5 binary
-*.png binary
-*.jpg binary
-*.pdf binary
-*.zip binary
-*.bin binary
-*.mem binary
-*.hex binary
-*.vvp binary
-*.s2p binary
-*.s3p binary
-*.step binary
-*.FCStd binary
-*.FCBak binary
@@ -8,109 +8,64 @@ on:

 jobs:
  # ===========================================================================
-  # Python: lint (ruff), syntax check (py_compile), unit tests (pytest)
-  # CI structure proposed by hcm444 — uses uv for dependency management
+  # Job 1: Python Host Software Tests (58 tests)
+  # radar_protocol, radar_dashboard, FT2232H connection, replay, opcodes, e2e
  # ===========================================================================
  python-tests:
-    name: Python Lint + Tests
+    name: Python Dashboard Tests (58)
    runs-on: ubuntu-latest

    steps:
-      - uses: actions/checkout@v4
+      - name: Checkout repository
+        uses: actions/checkout@v4

-      - uses: actions/setup-python@v5
+      - name: Set up Python 3.12
+        uses: actions/setup-python@v5
        with:
          python-version: "3.12"

-      - uses: astral-sh/setup-uv@v5
-
      - name: Install dependencies
-        run: uv sync --group dev
-
-      - name: Ruff lint (whole repo)
-        run: uv run ruff check .
-
-      - name: Syntax check (py_compile)
        run: |
-          uv run python - <<'PY'
-          import py_compile
-          from pathlib import Path
+          python -m pip install --upgrade pip
+          pip install pytest numpy h5py

-          skip = {".git", "__pycache__", ".venv", "venv", "docs"}
-          for p in Path(".").rglob("*.py"):
-              if skip & set(p.parts):
-                  continue
-              py_compile.compile(str(p), doraise=True)
-          PY
-
-      - name: Unit tests
-        run: >
-          uv run pytest
-          9_Firmware/9_3_GUI/test_GUI_V65_Tk.py
-          9_Firmware/9_3_GUI/test_v7.py
-          -v --tb=short
+      - name: Run test suite
+        run: python -m pytest 9_Firmware/9_3_GUI/test_radar_dashboard.py -v --tb=short

  # ===========================================================================
-  # MCU Firmware Unit Tests (20 tests)
+  # Job 2: MCU Firmware Unit Tests (20 tests)
  # Bug regression (15) + Gap-3 safety tests (5)
  # ===========================================================================
  mcu-tests:
-    name: MCU Firmware Tests
+    name: MCU Firmware Tests (20)
    runs-on: ubuntu-latest

    steps:
-      - uses: actions/checkout@v4
+      - name: Checkout repository
+        uses: actions/checkout@v4

      - name: Install build tools
        run: sudo apt-get update && sudo apt-get install -y build-essential

      - name: Build and run MCU tests
-        run: make test
        working-directory: 9_Firmware/9_1_Microcontroller/tests
+        run: make test

  # ===========================================================================
-  # FPGA RTL Regression (25 testbenches + lint)
+  # Job 3: FPGA RTL Regression (23 testbenches + lint)
+  # Phase 0: Vivado-style lint, Phase 1-4: unit + integration + e2e
  # ===========================================================================
  fpga-regression:
-    name: FPGA Regression
+    name: FPGA Regression (23 TBs + lint)
    runs-on: ubuntu-latest

    steps:
-      - uses: actions/checkout@v4
+      - name: Checkout repository
+        uses: actions/checkout@v4

      - name: Install Icarus Verilog
        run: sudo apt-get update && sudo apt-get install -y iverilog

      - name: Run full FPGA regression
-        run: bash run_regression.sh
        working-directory: 9_Firmware/9_2_FPGA
-
-  # ===========================================================================
-  # Cross-Layer Contract Tests (Python ↔ Verilog ↔ C)
-  # Validates opcode maps, bit widths, packet layouts, and round-trip
-  # correctness across FPGA RTL, Python GUI, and STM32 firmware.
-  # ===========================================================================
-  cross-layer-tests:
-    name: Cross-Layer Contract Tests
-    runs-on: ubuntu-latest
-
-    steps:
-      - uses: actions/checkout@v4
-
-      - uses: actions/setup-python@v5
-        with:
-          python-version: "3.12"
-
-      - uses: astral-sh/setup-uv@v5
-
-      - name: Install dependencies
-        run: uv sync --group dev
-
-      - name: Install Icarus Verilog
-        run: sudo apt-get update && sudo apt-get install -y iverilog
-
-      - name: Run cross-layer contract tests
-        run: >
-          uv run pytest
-          9_Firmware/tests/cross_layer/test_cross_layer_contract.py
-          -v --tb=short
+        run: bash run_regression.sh
@@ -32,12 +32,6 @@
 9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
-9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
-9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
-9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
-
-# Golden reference outputs (regenerated by testbenches)
-9_Firmware/9_2_FPGA/tb/golden/

 # macOS
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@@ -1,50 +0,0 @@
-Generated by EAGLE CAM Processor 7.4.0
-
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-
- Date              : 06/04/2026 22:10
- Drills            : generated
- Device            : Excellon drill station, coordinate format 2.5 inch
-
-Parameter settings:
-
- Tolerance Drill + :  2.50 %
- Tolerance Drill - :  2.50 %
- Rotate            : no
- Mirror            : no
- Optimize          : yes
- Auto fit          : yes
- OffsetX           : 0inch
- OffsetY           : 0inch
- Layers            : Drills Holes
-
-Drill File Info:
-
- Data Mode         : Absolute
- Units             : 1/100000 Inch
-
-Drills used:
-
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-
- T01   0.0059inch  1609
- T02   0.0079inch  1892
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- T13   0.0470inch   148
- T14   0.0472inch     4
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-
-Total number of drills: 4438
-
-Plotfiles:
-
- C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.drd
@@ -1,14 +0,0 @@
-T01 0.006in
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@@ -1,37 +0,0 @@
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-
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-
- Date              : 06/04/2026 22:41
- Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.bsk
- Apertures         : generated: 
- Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
-
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-
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- Tolerance Draw  + :  0.00 %
- Tolerance Draw  - :  0.00 %
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- Tolerance Flash - :  0.00 %
- Rotate            : no
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- Optimize          : yes
- Auto fit          : yes
- OffsetX           : 0inch
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-
- D10      draw      0.0030inch             121
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-R52 26.11 183.12 270 4.7k R0201
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@@ -1,105 +0,0 @@
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-"2";"12pF";"CC0201";"C0201";"C184, C185";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
-"37";"142-0731-211";"142-0731-211";"1420731211";"J1, J18, J20, J22, J23, J24, J25, J26, J27, J28, J29, J30, J31, J32, J33, J34, J35, J36, J37, J38, J39, J40, J41, J42, J43, J44, J45, J46, J47, J48, J49, J50, J51, J52, J53, J54, J55";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"";"";"";"";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"9.8852mm";"Cinch Connectivity Solutions";"142-0731-211";"";"";"530-142-0731-211";"https://www.mouser.co.uk/ProductDetail/Johnson-Cinch-Connectivity-Solutions/142-0731-211?qs=HFfMDpzxxd0OVzI3hm9tuA%3D%3D";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
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-"49";"1k";"RR0201";"R0201";"R41, R43, R55, R56, R57, R58, R59, R61, R82, R85, R86, R87, R88, R93, R94, R99, R100, R101, R102, R107, R108, R109, R118, R124, R125, R126, R127, R128, R129, R130, R131, R133, R134, R135, R136, R137, R138, R139, R140, R144, R147, R148, R149, R167, R168, R169, R170, R171, R172";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
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-"51";"1pF";"CC0201";"C0201";"C70, C71, C72, C83, C84, C85, C126, C128, C129, C134, C135, C136, C142, C143, C144, C149, C150, C151, C163, C165, C166, C171, C172, C173, C197, C198, C199, C204, C205, C206, C211, C212, C213, C218, C219, C220, C225, C226, C227, C232, C233, C234, C239, C240, C241, C246, C247, C248, C253, C254, C255";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
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-"16";"2.443k";"RR0201";"R0201";"R89, R90, R91, R92, R95, R96, R97, R98, R103, R104, R105, R106, R119, R120, R121, R122";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
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-"4";"200R";"RR0201";"R0201";"R16, R17, R20, R21";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
-"1";"20k";"R-EU_R0402";"R0402";"R38";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
-"40";"22-23-2021";"22-23-2021";"22-23-2021";"X1, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X24, X54, X55, X56, X_1, X_2, X_3, X_4, X_5, X_6, X_7, X_8, X_9, X_10, X_11, X_12, X_13, X_14, X_15, X_16";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"";"";"";"MOLEX";"";"";"";"";"22-23-2021";"1462926";"25C3832";"";"40";"";"";"";"";"";"";"";"";
-"16";"22-23-2031";"22-23-2031";"22-23-2031";"X3, X38, X39, X40, X41, X42, X43, X44, X45, X46, X47, X48, X49, X50, X51, X52";".100" (2.54mm) Center Header - 3 Pin";"";"";"";"";"";"";"";"";"MOLEX";"";"";"";"";"22-23-2031";"1462950";"30C0862";"";"35";"";"";"";"";"";"";"";"";
-"11";"22.1k";"RR0201";"R0201";"R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
-"13";"22R";"RR0201";"R0201";"R23, R24, R25, R26, R27, R28, R29, R30, R49, R51, R62, R63, R64";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
-"2";"22pF";"CC0201";"C0201";"C308, C309";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
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-"2";"24R";"R-EU_R0402";"R0402";"R1, R13";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
-"2";"25R";"RR0201";"R0201";"R165, R166";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
-"4";"25pF";"CC0201";"C0201";"C64, C65, C268, C270";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
-"1";"3.3uF";"CC0201";"C0201";"C191";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
-"2";"32.8pF";"CC0201";"C0201";"C59, C127";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
-"1";"3k2";"RR0201";"R0201";"R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
-"2";"4.3k";"R-EU_R0201";"R0201";"R15, R32";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
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-"8";"4.7uF";"CC0201";"C0201";"C108, C109, C153, C154, C177, C178, C287, C289";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
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-"2";"DAC5578SRGET";"DAC5578SRGET";"RGE24_2P7X2P7";"U7, U69";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/dac5578";"8-bit, Octal Channel, Ultra-Low Glitch, Voltage Output, 2-Wire Interface DAC 24-VQFN -40 to 125";"";"Texas Instruments";"DAC5578SRGET";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"ECS-120-10-36B2-JTN-TR";"CRYSTAL-12MHZ";"CRYSTAL-SMD-2X2.5MM";"Y1";"12.0MHz Crystal";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"XTAL-15540";"";"";"";"";"";"";
-"1";"EP4RKU+";"EP4RKU+";"DG1677-2_MNC";"U16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"EP4RKU+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"FT2232HQ";"FT2232HQ";"64QFN_FT2232HQ_FTD";"U6";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"";"";"FT2232HQ";"";"FTDI, Future Technology Devices International Ltd";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"16";"INA241A3IDGKRDGK0008A-MFG";"INA241A3IDGKRDGK0008A-MFG";"DGK0008A-MFG";"U11, U73, U74, U75, U76, U77, U78, U79, U80, U81, U82, U83, U84, U85, U86, U87";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"-5-V to 110-V bidirectional ultraprecise current sense amplifier with enhanced PWM rejection 8-VSSOP -40 to 125";"";"Texas Instruments";"INA241A3IDGKR";"";"";"";"";"";"";"";"";"";"";"";"";"RefDes";"";"";"";"TYPE";"";
-"2";"LTC5552IUDBTRMPBF";"LTC5552IUDBTRMPBF";"UDB_12_ADI";"U5, U13";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LTC5552IUDB#TRMPBF";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"17";"M3SWA2-34DR+";"M3SWA2-34DR+";"16_QFN";"RF_SW_1, RF_SW_2, RF_SW_3, RF_SW_4, RF_SW_5, RF_SW_6, RF_SW_7, RF_SW_8, RF_SW_9, RF_SW_10, RF_SW_11, RF_SW_12, RF_SW_13, RF_SW_14, RF_SW_15, RF_SW_16, U$1";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"2";"MINI-USB-32005-201";"MINI-USB-32005-201";"32005-201";"X2, X53";"MINI USB-B Conector";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"";"5";"";"";"";"";"";"";"";"";
-"1";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"TACTILE_SWITCH_SMD_4.6X2.8MM";"S1";"Momentary Switch (Pushbutton) - SPST";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"SWCH-15606";"";"";"";"";"";"";
-"1";"MT25QL01GBBB8E12-0AUT";"MT25QL01GBBB8E12-0AUT";"BGA24_MT25QL_MRN";"U9";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"MT25QL01GBBB8E12-0AUT";"";"Micron";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"NX3215SA-32.768KHz";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"NX3225GD-8MHZ-STD-CRA-3";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL1";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"4";"OPA4703EA/250";"OPA4703EA/250";"PW14";"OPA_1, OPA_2, OPA_3, OPA_4";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/opa4703";"Quad, 12-V, 1-MHz, low-offset operational amplifier 14-TSSOP -40 to 85";"";"Texas Instruments";"OPA4703EA/250";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"STM32F746ZGT7";"STM32F746ZGT7";"LQFP-144_STM";"U2";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"STM32F746ZGT7";"";"STMicroelectronics";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"34";"SZMMSZ5232BT1G";"SZMMSZ5232BT1G";"SOD-123_ONS";"U14, U15, U17, U37, U38, U39, U40, U41, U43, U44, U45, U46, U47, U48, U49, U50, U51, U52, U53, U54, U55, U56, U57, U58, U59, U60, U61, U62, U63, U64, U65, U66, U67, U68";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"SZMMSZ5232BT1G";"";"onsemi";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
-"1";"XC7A50T-2FTG256I";"XC7A50T-2FTG256I";"BGA256C100P16X16_1700X1700X155";"U42";"Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA  Check availability";"In Stock";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=eda";"";"";"                                                      Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA                                              ";"";"";"";"Xilinx Inc.";"";"";"";"XC7A50T-2FTG256I";"";"";"";"LBGA-256 Xilinx Inc.";"";"None";"";"";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=snap";"";"";"";"";
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@@ -1,438 +0,0 @@
-#!/usr/bin/env python3
-"""
-AERIS-10 FMC Anti-Alias Filter — openEMS 3D EM Simulation
-==========================================================
-5th-order differential Butterworth LC LPF, fc ≈ 195 MHz
-All components are 0402 (1.0 x 0.5 mm) on FR4 4-layer stackup.
-
-Filter topology (each half of differential):
-  IN → R_series(49.9Ω) → L1(24nH) → C1(27pF)↓GND → L2(82nH) → C2(27pF)↓GND → L3(24nH) → OUT
-  Plus R_diff(100Ω) across input and output differential pairs.
-
-PCB stackup:
-  L1: F.Cu    (signal + components)  — 35µm copper
-  Prepreg: 0.2104 mm
-  L2: In1.Cu  (GND plane)           — 35µm copper
-  Core: 1.0 mm
-  L3: In2.Cu  (Power plane)         — 35µm copper
-  Prepreg: 0.2104 mm
-  L4: B.Cu    (signal)              — 35µm copper
-
-Total board thickness ≈ 1.6 mm
-
-Differential trace: W=0.23mm, S=0.12mm gap → Zdiff≈100Ω
-All 0402 pads: 0.5mm x 0.55mm with 0.5mm gap between pads
-
-Simulation extracts 4-port S-parameters (differential in → differential out)
-then converts to mixed-mode (Sdd11, Sdd21, Scc21) for analysis.
-"""
-
-import os
-import sys
-import numpy as np
-
-sys.path.insert(0, '/Users/ganeshpanth/openEMS-Project/CSXCAD/python')
-sys.path.insert(0, '/Users/ganeshpanth/openEMS-Project/openEMS/python')
-os.environ['PATH'] = '/Users/ganeshpanth/opt/openEMS/bin:' + os.environ.get('PATH', '')
-
-from CSXCAD import ContinuousStructure
-from openEMS import openEMS
-from openEMS.physical_constants import C0, EPS0
-
-unit = 1e-3
-
-f_start = 1e6
-f_stop = 1e9
-f_center = 150e6
-f_IF_low = 120e6
-f_IF_high = 180e6
-
-max_res = C0 / f_stop / unit / 20
-
-copper_t = 0.035
-prepreg_t = 0.2104
-core_t = 1.0
-sub_er = 4.3
-sub_tand = 0.02
-cu_cond = 5.8e7
-
-z_L4_bot = 0.0
-z_L4_top = z_L4_bot + copper_t
-z_pre2_top = z_L4_top + prepreg_t
-z_L3_top = z_pre2_top + copper_t
-z_core_top = z_L3_top + core_t
-z_L2_top = z_core_top + copper_t
-z_pre1_top = z_L2_top + prepreg_t
-z_L1_bot = z_pre1_top
-z_L1_top = z_L1_bot + copper_t
-
-pad_w = 0.50
-pad_l = 0.55
-pad_gap = 0.50
-comp_pitch = 1.5
-
-trace_w = 0.23
-trace_s = 0.12
-pair_pitch = trace_w + trace_s
-
-R_series = 49.9
-R_diff_in = 100.0
-R_diff_out = 100.0
-
-L1_val = 24e-9
-L2_val = 82e-9
-L3_val = 24e-9
-
-C1_val = 27e-12
-C2_val = 27e-12
-
-FDTD = openEMS(NrTS=50000, EndCriteria=1e-5)
-FDTD.SetGaussExcite(0.5 * (f_start + f_stop), 0.5 * (f_stop - f_start))
-FDTD.SetBoundaryCond(['PML_8'] * 6)
-
-CSX = ContinuousStructure()
-FDTD.SetCSX(CSX)
-
-copper = CSX.AddMetal('copper')
-gnd_metal = CSX.AddMetal('gnd_plane')
-fr4_pre1 = CSX.AddMaterial(
-    'prepreg1', epsilon=sub_er, kappa=sub_tand * 2 * np.pi * f_center * EPS0 * sub_er
-)
-fr4_core = CSX.AddMaterial(
-    'core', epsilon=sub_er, kappa=sub_tand * 2 * np.pi * f_center * EPS0 * sub_er
-)
-fr4_pre2 = CSX.AddMaterial(
-    'prepreg2', epsilon=sub_er, kappa=sub_tand * 2 * np.pi * f_center * EPS0 * sub_er
-)
-
-y_P = +pair_pitch / 2
-y_N = -pair_pitch / 2
-
-x_port_in = -1.0
-x_R_series = 0.0
-x_L1 = x_R_series + comp_pitch
-x_C1 = x_L1 + comp_pitch
-x_L2 = x_C1 + comp_pitch
-x_C2 = x_L2 + comp_pitch
-x_L3 = x_C2 + comp_pitch
-x_port_out = x_L3 + comp_pitch + 1.0
-
-x_Rdiff_in = x_port_in - 0.5
-x_Rdiff_out = x_port_out + 0.5
-
-margin = 3.0
-x_min = x_Rdiff_in - margin
-x_max = x_Rdiff_out + margin
-y_min = y_N - margin
-y_max = y_P + margin
-z_min = z_L4_bot - margin
-z_max = z_L1_top + margin
-
-fr4_pre1.AddBox([x_min, y_min, z_L2_top], [x_max, y_max, z_L1_bot], priority=1)
-fr4_core.AddBox([x_min, y_min, z_L3_top], [x_max, y_max, z_core_top], priority=1)
-fr4_pre2.AddBox([x_min, y_min, z_L4_top], [x_max, y_max, z_pre2_top], priority=1)
-
-gnd_metal.AddBox(
-    [x_min + 0.5, y_min + 0.5, z_core_top], [x_max - 0.5, y_max - 0.5, z_L2_top], priority=10
-)
-
-
-def add_trace_segment(x_start, x_end, y_center, z_bot, z_top, w, metal, priority=20):
-    metal.AddBox(
-        [x_start, y_center - w / 2, z_bot], [x_end, y_center + w / 2, z_top], priority=priority
-    )
-
-
-def add_0402_pads(x_center, y_center, z_bot, z_top, metal, priority=20):
-    x_left = x_center - pad_gap / 2 - pad_w / 2
-    metal.AddBox(
-        [x_left - pad_w / 2, y_center - pad_l / 2, z_bot],
-        [x_left + pad_w / 2, y_center + pad_l / 2, z_top],
-        priority=priority,
-    )
-    x_right = x_center + pad_gap / 2 + pad_w / 2
-    metal.AddBox(
-        [x_right - pad_w / 2, y_center - pad_l / 2, z_bot],
-        [x_right + pad_w / 2, y_center + pad_l / 2, z_top],
-        priority=priority,
-    )
-    return (x_left, x_right)
-
-
-def add_lumped_element(
-    CSX, name, element_type, value, x_center, y_center, z_bot, z_top, direction='x'
-):
-    x_left = x_center - pad_gap / 2 - pad_w / 2
-    x_right = x_center + pad_gap / 2 + pad_w / 2
-    if direction == 'x':
-        start = [x_left, y_center - pad_l / 4, z_bot]
-        stop = [x_right, y_center + pad_l / 4, z_top]
-        edir = 'x'
-    elif direction == 'y':
-        start = [x_center - pad_l / 4, y_center - pad_gap / 2 - pad_w / 2, z_bot]
-        stop = [x_center + pad_l / 4, y_center + pad_gap / 2 + pad_w / 2, z_top]
-        edir = 'y'
-    if element_type == 'R':
-        elem = CSX.AddLumpedElement(name, ny=edir, caps=True, R=value)
-    elif element_type == 'L':
-        elem = CSX.AddLumpedElement(name, ny=edir, caps=True, L=value)
-    elif element_type == 'C':
-        elem = CSX.AddLumpedElement(name, ny=edir, caps=True, C=value)
-    elem.AddBox(start, stop, priority=30)
-    return elem
-
-
-def add_shunt_cap(
-    CSX, name, value, x_center, y_trace, _z_top_signal, _z_gnd_top, metal, priority=20,
-):
-    metal.AddBox(
-        [x_center - pad_w / 2, y_trace - pad_l / 2, z_L1_bot],
-        [x_center + pad_w / 2, y_trace + pad_l / 2, z_L1_top],
-        priority=priority,
-    )
-    via_drill = 0.15
-    cap = CSX.AddLumpedElement(name, ny='z', caps=True, C=value)
-    cap.AddBox(
-        [x_center - via_drill, y_trace - via_drill, z_L2_top],
-        [x_center + via_drill, y_trace + via_drill, z_L1_bot],
-        priority=30,
-    )
-    via_metal = CSX.AddMetal(name + '_via')
-    via_metal.AddBox(
-        [x_center - via_drill, y_trace - via_drill, z_L2_top],
-        [x_center + via_drill, y_trace + via_drill, z_L1_bot],
-        priority=25,
-    )
-
-
-add_trace_segment(
-    x_port_in, x_R_series - pad_gap / 2 - pad_w, y_P, z_L1_bot, z_L1_top, trace_w, copper
-)
-add_0402_pads(x_R_series, y_P, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'R10', 'R', R_series, x_R_series, y_P, z_L1_bot, z_L1_top)
-add_trace_segment(
-    x_R_series + pad_gap / 2 + pad_w,
-    x_L1 - pad_gap / 2 - pad_w,
-    y_P,
-    z_L1_bot,
-    z_L1_top,
-    trace_w,
-    copper,
-)
-add_0402_pads(x_L1, y_P, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L5', 'L', L1_val, x_L1, y_P, z_L1_bot, z_L1_top)
-add_trace_segment(x_L1 + pad_gap / 2 + pad_w, x_C1, y_P, z_L1_bot, z_L1_top, trace_w, copper)
-add_shunt_cap(CSX, 'C53', C1_val, x_C1, y_P, z_L1_top, z_L2_top, copper)
-add_trace_segment(x_C1, x_L2 - pad_gap / 2 - pad_w, y_P, z_L1_bot, z_L1_top, trace_w, copper)
-add_0402_pads(x_L2, y_P, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L8', 'L', L2_val, x_L2, y_P, z_L1_bot, z_L1_top)
-add_trace_segment(x_L2 + pad_gap / 2 + pad_w, x_C2, y_P, z_L1_bot, z_L1_top, trace_w, copper)
-add_shunt_cap(CSX, 'C55', C2_val, x_C2, y_P, z_L1_top, z_L2_top, copper)
-add_trace_segment(x_C2, x_L3 - pad_gap / 2 - pad_w, y_P, z_L1_bot, z_L1_top, trace_w, copper)
-add_0402_pads(x_L3, y_P, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L10', 'L', L3_val, x_L3, y_P, z_L1_bot, z_L1_top)
-add_trace_segment(x_L3 + pad_gap / 2 + pad_w, x_port_out, y_P, z_L1_bot, z_L1_top, trace_w, copper)
-
-add_trace_segment(
-    x_port_in, x_R_series - pad_gap / 2 - pad_w, y_N, z_L1_bot, z_L1_top, trace_w, copper
-)
-add_0402_pads(x_R_series, y_N, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'R11', 'R', R_series, x_R_series, y_N, z_L1_bot, z_L1_top)
-add_trace_segment(
-    x_R_series + pad_gap / 2 + pad_w,
-    x_L1 - pad_gap / 2 - pad_w,
-    y_N,
-    z_L1_bot,
-    z_L1_top,
-    trace_w,
-    copper,
-)
-add_0402_pads(x_L1, y_N, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L6', 'L', L1_val, x_L1, y_N, z_L1_bot, z_L1_top)
-add_trace_segment(x_L1 + pad_gap / 2 + pad_w, x_C1, y_N, z_L1_bot, z_L1_top, trace_w, copper)
-add_shunt_cap(CSX, 'C54', C1_val, x_C1, y_N, z_L1_top, z_L2_top, copper)
-add_trace_segment(x_C1, x_L2 - pad_gap / 2 - pad_w, y_N, z_L1_bot, z_L1_top, trace_w, copper)
-add_0402_pads(x_L2, y_N, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L7', 'L', L2_val, x_L2, y_N, z_L1_bot, z_L1_top)
-add_trace_segment(x_L2 + pad_gap / 2 + pad_w, x_C2, y_N, z_L1_bot, z_L1_top, trace_w, copper)
-add_shunt_cap(CSX, 'C56', C2_val, x_C2, y_N, z_L1_top, z_L2_top, copper)
-add_trace_segment(x_C2, x_L3 - pad_gap / 2 - pad_w, y_N, z_L1_bot, z_L1_top, trace_w, copper)
-add_0402_pads(x_L3, y_N, z_L1_bot, z_L1_top, copper)
-add_lumped_element(CSX, 'L9', 'L', L3_val, x_L3, y_N, z_L1_bot, z_L1_top)
-add_trace_segment(x_L3 + pad_gap / 2 + pad_w, x_port_out, y_N, z_L1_bot, z_L1_top, trace_w, copper)
-
-R4_x = x_port_in - 0.3
-copper.AddBox(
-    [R4_x - pad_l / 2, y_P - pad_w / 2, z_L1_bot],
-    [R4_x + pad_l / 2, y_P + pad_w / 2, z_L1_top],
-    priority=20,
-)
-copper.AddBox(
-    [R4_x - pad_l / 2, y_N - pad_w / 2, z_L1_bot],
-    [R4_x + pad_l / 2, y_N + pad_w / 2, z_L1_top],
-    priority=20,
-)
-R4_elem = CSX.AddLumpedElement('R4', ny='y', caps=True, R=R_diff_in)
-R4_elem.AddBox([R4_x - pad_l / 4, y_N, z_L1_bot], [R4_x + pad_l / 4, y_P, z_L1_top], priority=30)
-
-R18_x = x_port_out + 0.3
-copper.AddBox(
-    [R18_x - pad_l / 2, y_P - pad_w / 2, z_L1_bot],
-    [R18_x + pad_l / 2, y_P + pad_w / 2, z_L1_top],
-    priority=20,
-)
-copper.AddBox(
-    [R18_x - pad_l / 2, y_N - pad_w / 2, z_L1_bot],
-    [R18_x + pad_l / 2, y_N + pad_w / 2, z_L1_top],
-    priority=20,
-)
-R18_elem = CSX.AddLumpedElement('R18', ny='y', caps=True, R=R_diff_out)
-R18_elem.AddBox([R18_x - pad_l / 4, y_N, z_L1_bot], [R18_x + pad_l / 4, y_P, z_L1_top], priority=30)
-
-port1 = FDTD.AddLumpedPort(
-    1,
-    50,
-    [x_port_in, y_P - trace_w / 2, z_L2_top],
-    [x_port_in, y_P + trace_w / 2, z_L1_bot],
-    'z',
-    excite=1.0,
-)
-port2 = FDTD.AddLumpedPort(
-    2,
-    50,
-    [x_port_in, y_N - trace_w / 2, z_L2_top],
-    [x_port_in, y_N + trace_w / 2, z_L1_bot],
-    'z',
-    excite=-1.0,
-)
-port3 = FDTD.AddLumpedPort(
-    3,
-    50,
-    [x_port_out, y_P - trace_w / 2, z_L2_top],
-    [x_port_out, y_P + trace_w / 2, z_L1_bot],
-    'z',
-    excite=0,
-)
-port4 = FDTD.AddLumpedPort(
-    4,
-    50,
-    [x_port_out, y_N - trace_w / 2, z_L2_top],
-    [x_port_out, y_N + trace_w / 2, z_L1_bot],
-    'z',
-    excite=0,
-)
-
-mesh = CSX.GetGrid()
-mesh.SetDeltaUnit(unit)
-mesh.AddLine('x', [x_min, x_max])
-for x_comp in [x_R_series, x_L1, x_C1, x_L2, x_C2, x_L3]:
-    mesh.AddLine('x', np.linspace(x_comp - 1.0, x_comp + 1.0, 15))
-mesh.AddLine('x', [x_port_in, x_port_out])
-mesh.AddLine('x', [R4_x, R18_x])
-mesh.AddLine('y', [y_min, y_max])
-for y_trace in [y_P, y_N]:
-    mesh.AddLine('y', np.linspace(y_trace - 0.5, y_trace + 0.5, 10))
-mesh.AddLine('z', [z_min, z_max])
-mesh.AddLine('z', np.linspace(z_L4_bot - 0.1, z_L1_top + 0.1, 25))
-mesh.SmoothMeshLines('x', max_res, ratio=1.4)
-mesh.SmoothMeshLines('y', max_res, ratio=1.4)
-mesh.SmoothMeshLines('z', max_res / 3, ratio=1.3)
-
-sim_path = os.path.join(os.path.dirname(os.path.abspath(__file__)), 'results')
-if not os.path.exists(sim_path):
-    os.makedirs(sim_path)
-
-CSX_file = os.path.join(sim_path, 'aaf_filter.xml')
-CSX.Write2XML(CSX_file)
-
-FDTD.Run(sim_path, cleanup=True, verbose=3)
-
-freq = np.linspace(f_start, f_stop, 1001)
-port1.CalcPort(sim_path, freq)
-port2.CalcPort(sim_path, freq)
-port3.CalcPort(sim_path, freq)
-port4.CalcPort(sim_path, freq)
-
-inc1 = port1.uf_inc
-ref1 = port1.uf_ref
-inc2 = port2.uf_inc
-ref2 = port2.uf_ref
-inc3 = port3.uf_inc
-ref3 = port3.uf_ref
-inc4 = port4.uf_inc
-ref4 = port4.uf_ref
-
-a_diff = (inc1 - inc2) / np.sqrt(2)
-b_diff_in = (ref1 - ref2) / np.sqrt(2)
-b_diff_out = (ref3 - ref4) / np.sqrt(2)
-
-Sdd11 = b_diff_in / a_diff
-Sdd21 = b_diff_out / a_diff
-
-b_comm_out = (ref3 + ref4) / np.sqrt(2)
-Scd21 = b_comm_out / a_diff
-
-import matplotlib  # noqa: E402
-matplotlib.use('Agg')
-import matplotlib.pyplot as plt  # noqa: E402
-
-fig, axes = plt.subplots(3, 1, figsize=(12, 14))
-
-ax = axes[0]
-Sdd21_dB = 20 * np.log10(np.abs(Sdd21) + 1e-15)
-ax.plot(freq / 1e6, Sdd21_dB, 'b-', linewidth=2, label='|Sdd21| (Insertion Loss)')
-ax.axvspan(
-    f_IF_low / 1e6, f_IF_high / 1e6, alpha=0.15, color='green', label='IF Band (120-180 MHz)'
-)
-ax.axhline(-3, color='r', linestyle='--', alpha=0.5, label='-3 dB')
-ax.set_xlabel('Frequency (MHz)')
-ax.set_ylabel('|Sdd21| (dB)')
-ax.set_title('Anti-Alias Filter — Differential Insertion Loss')
-ax.set_xlim([0, 1000])
-ax.set_ylim([-60, 5])
-ax.grid(True, alpha=0.3)
-ax.legend()
-
-ax = axes[1]
-Sdd11_dB = 20 * np.log10(np.abs(Sdd11) + 1e-15)
-ax.plot(freq / 1e6, Sdd11_dB, 'r-', linewidth=2, label='|Sdd11| (Return Loss)')
-ax.axvspan(f_IF_low / 1e6, f_IF_high / 1e6, alpha=0.15, color='green', label='IF Band')
-ax.axhline(-10, color='orange', linestyle='--', alpha=0.5, label='-10 dB')
-ax.set_xlabel('Frequency (MHz)')
-ax.set_ylabel('|Sdd11| (dB)')
-ax.set_title('Anti-Alias Filter — Differential Return Loss')
-ax.set_xlim([0, 1000])
-ax.set_ylim([-40, 0])
-ax.grid(True, alpha=0.3)
-ax.legend()
-
-ax = axes[2]
-phase_Sdd21 = np.unwrap(np.angle(Sdd21))
-group_delay = -np.diff(phase_Sdd21) / np.diff(2 * np.pi * freq) * 1e9
-ax.plot(freq[1:] / 1e6, group_delay, 'g-', linewidth=2, label='Group Delay')
-ax.axvspan(f_IF_low / 1e6, f_IF_high / 1e6, alpha=0.15, color='green', label='IF Band')
-ax.set_xlabel('Frequency (MHz)')
-ax.set_ylabel('Group Delay (ns)')
-ax.set_title('Anti-Alias Filter — Group Delay')
-ax.set_xlim([0, 500])
-ax.grid(True, alpha=0.3)
-ax.legend()
-
-plt.tight_layout()
-plot_file = os.path.join(sim_path, 'aaf_filter_response.png')
-plt.savefig(plot_file, dpi=150)
-
-idx_120 = np.argmin(np.abs(freq - f_IF_low))
-idx_150 = np.argmin(np.abs(freq - f_center))
-idx_180 = np.argmin(np.abs(freq - f_IF_high))
-idx_200 = np.argmin(np.abs(freq - 200e6))
-idx_400 = np.argmin(np.abs(freq - 400e6))
-
-
-csv_file = os.path.join(sim_path, 'aaf_sparams.csv')
-np.savetxt(
-    csv_file,
-    np.column_stack([freq / 1e6, Sdd21_dB, Sdd11_dB, 20 * np.log10(np.abs(Scd21) + 1e-15)]),
-    header='Freq_MHz, Sdd21_dB, Sdd11_dB, Scd21_dB',
-    delimiter=',', fmt='%.6f'
-)
@@ -91,9 +91,9 @@ z_edges = np.concatenate([z_centers - slot_L/2.0, z_centers + slot_L/2.0])
 # -------------------------
 # Mesh lines — EXPLICIT (no GetLine calls)
 # -------------------------
-x_lines = sorted({x_min, -t_metal, 0.0, a, a + t_metal, x_max, *list(x_edges)})
+x_lines = sorted(set([x_min, -t_metal, 0.0, a, a+t_metal, x_max] + list(x_edges)))
 y_lines = [y_min, 0.0, b, b+t_metal, y_max]
-z_lines = sorted({z_min, 0.0, L, z_max, *list(z_edges)})
+z_lines = sorted(set([z_min, 0.0, L, z_max] + list(z_edges)))

 mesh.AddLine('x', x_lines)
 mesh.AddLine('y', y_lines)
@@ -106,8 +106,7 @@ mesh.SmoothMeshLines('all', mesh_res, ratio=1.4)
 # Materials
 # -------------------------
 pec    = CSX.AddMetal('PEC')
-quartz = CSX.AddMaterial('QUARTZ')
-quartz.SetMaterialProperty(epsilon=er_quartz)
+quartz = CSX.AddMaterial('QUARTZ'); quartz.SetMaterialProperty(epsilon=er_quartz)
 air    = CSX.AddMaterial('AIR')     # explicit for slot holes

 # -------------------------
@@ -123,7 +122,7 @@ pec.AddBox([-t_metal,-t_metal,0],[a+t_metal,0,       L])          # bottom
 pec.AddBox([-t_metal, b, 0],     [a+t_metal,b+t_metal,L])         # top

 # Slots = AIR boxes overriding the top metal
-for zc, xc in zip(z_centers, x_centers, strict=False):
+for zc, xc in zip(z_centers, x_centers):
    x1, x2 = xc - slot_w/2.0, xc + slot_w/2.0
    z1, z2 = zc - slot_L/2.0, zc + slot_L/2.0
    prim = air.AddBox([x1, b, z1], [x2, b+t_metal, z2])
@@ -181,7 +180,7 @@ if simulate:
 # Post-processing: S-params & impedance
 # -------------------------
 freq = np.linspace(f_start, f_stop, 401)
-ports = list(FDTD.ports)   # Port 1 & Port 2 in creation order
+ports = [p for p in FDTD.ports]   # Port 1 & Port 2 in creation order
 for p in ports:
    p.CalcPort(Sim_Path, freq)

@@ -192,19 +191,13 @@ Zin = ports[0].uf_tot / ports[0].if_tot
 plt.figure(figsize=(7.6,4.6))
 plt.plot(freq*1e-9, 20*np.log10(np.abs(S11)), lw=2, label='|S11|')
 plt.plot(freq*1e-9, 20*np.log10(np.abs(S21)), lw=2, ls='--', label='|S21|')
-plt.grid(True)
-plt.legend()
-plt.xlabel('Frequency (GHz)')
-plt.ylabel('Magnitude (dB)')
+plt.grid(True); plt.legend(); plt.xlabel('Frequency (GHz)'); plt.ylabel('Magnitude (dB)')
 plt.title('S-Parameters: Slotted Quartz-Filled WG')

 plt.figure(figsize=(7.6,4.6))
 plt.plot(freq*1e-9, np.real(Zin), lw=2, label='Re{Zin}')
 plt.plot(freq*1e-9, np.imag(Zin), lw=2, ls='--', label='Im{Zin}')
-plt.grid(True)
-plt.legend()
-plt.xlabel('Frequency (GHz)')
-plt.ylabel('Ohms')
+plt.grid(True); plt.legend(); plt.xlabel('Frequency (GHz)'); plt.ylabel('Ohms')
 plt.title('Input Impedance (Port 1)')

 # -------------------------
@@ -226,6 +219,9 @@ mismatch = 1.0 - np.abs(S11[idx_f0])**2   # (1 - |S11|^2)
 Gmax_lin = Dmax_lin * float(mismatch)
 Gmax_dBi = 10*np.log10(Gmax_lin)

+print(f"Max directivity @ {f0/1e9:.3f} GHz: {10*np.log10(Dmax_lin):.2f} dBi")
+print(f"Mismatch term  (1-|S11|^2)        : {float(mismatch):.3f}")
+print(f"Estimated max realized gain       : {Gmax_dBi:.2f} dBi")

 # 3D normalized pattern
 E = np.squeeze(res.E_norm)     # shape [f, th, ph] -> [th, ph]
@@ -241,26 +237,19 @@ ax = fig.add_subplot(111, projection='3d')
 ax.plot_surface(X, Y, Z, rstride=2, cstride=2, linewidth=0, antialiased=True, alpha=0.92)
 ax.set_title(f'Normalized 3D Pattern @ {f0/1e9:.2f} GHz\n(peak ≈ {Gmax_dBi:.1f} dBi)')
 ax.set_box_aspect((1,1,1))
-ax.set_xlabel('x')
-ax.set_ylabel('y')
-ax.set_zlabel('z')
+ax.set_xlabel('x'); ax.set_ylabel('y'); ax.set_zlabel('z')
 plt.tight_layout()

 # Quick 2D geometry preview (top view at y=b)
 plt.figure(figsize=(8.4,2.8))
-plt.fill_between(
-    [0, a], [0, 0], [L, L], color='#dddddd', alpha=0.5, step='pre', label='WG aperture (top)'
-)
-for zc, xc in zip(z_centers, x_centers, strict=False):
+plt.fill_between([0,a], [0,0], [L,L], color='#dddddd', alpha=0.5, step='pre', label='WG aperture (top)')
+for zc, xc in zip(z_centers, x_centers):
    plt.gca().add_patch(plt.Rectangle((xc - slot_w/2.0, zc - slot_L/2.0),
                                      slot_w, slot_L, fc='#3355ff', ec='k'))
-plt.xlim(-2, a + 2)
-plt.ylim(-5, L + 5)
+plt.xlim(-2, a+2); plt.ylim(-5, L+5)
 plt.gca().invert_yaxis()
-plt.xlabel('x (mm)')
-plt.ylabel('z (mm)')
+plt.xlabel('x (mm)'); plt.ylabel('z (mm)')
 plt.title('Top-view slot layout (y=b plane)')
-plt.grid(True)
-plt.legend()
+plt.grid(True); plt.legend()

 plt.show()
@@ -1,6 +1,6 @@
 # openems_quartz_slotted_wg_10p5GHz.py
 # Slotted rectangular waveguide (quartz-filled, εr=3.8) tuned to 10.5 GHz.
-# Builds geometry, meshes (no GetLine calls), sweeps S-params/impedance over 9.5-11.5 GHz,
+# Builds geometry, meshes (no GetLine calls), sweeps S-params/impedance over 9.5–11.5 GHz,
 # computes 3D far-field, and reports estimated max realized gain.

 import os
@@ -15,14 +15,14 @@ from openEMS.physical_constants import C0
 try:
    from CSXCAD import ContinuousStructure, AppCSXCAD_BIN
    HAVE_APP = True
-except ImportError:
+except Exception:
    from CSXCAD import ContinuousStructure
    AppCSXCAD_BIN = None
    HAVE_APP = False

 #Set PROFILE to "sanity" first; run and check [mesh] cells: stays reasonable.

-#If it's small, move to "balanced"; once happy, go "full".
+#If it’s small, move to "balanced"; once happy, go "full".

 #Toggle VIEW_GEOM=True if you want the 3D viewer (requires AppCSXCAD_BIN available).

@@ -123,9 +123,9 @@ x_edges = np.concatenate([x_centers - slot_w/2.0, x_centers + slot_w/2.0])
 z_edges = np.concatenate([z_centers - slot_L/2.0, z_centers + slot_L/2.0])

 # Mesh lines: explicit (NO GetLine calls)
-x_lines = sorted({x_min, -t_metal, 0.0, a, a + t_metal, x_max, *list(x_edges)})
+x_lines = sorted(set([x_min, -t_metal, 0.0, a, a+t_metal, x_max] + list(x_edges)))
 y_lines = [y_min, 0.0, b, b+t_metal, y_max]
-z_lines = sorted({z_min, 0.0, guide_length_mm, z_max, *list(z_edges)})
+z_lines = sorted(set([z_min, 0.0, guide_length_mm, z_max] + list(z_edges)))

 mesh.AddLine('x', x_lines)
 mesh.AddLine('y', y_lines)
@@ -134,10 +134,11 @@ mesh.AddLine('z', z_lines)
 # Print complexity and rough memory (to help stay inside 16 GB)
 Nx, Ny, Nz = len(x_lines)-1, len(y_lines)-1, len(z_lines)-1
 Ncells = Nx*Ny*Nz
+print(f"[mesh] cells: {Nx} × {Ny} × {Nz} = {Ncells:,}")
 mem_fields_bytes = Ncells * 6 * 8  # rough ~ (Ex,Ey,Ez,Hx,Hy,Hz) doubles
-dx_min = min(np.diff(x_lines))
-dy_min = min(np.diff(y_lines))
-dz_min = min(np.diff(z_lines))
+print(f"[mesh] rough field memory: ~{mem_fields_bytes/1e9:.2f} GB (solver overhead extra)")
+dx_min = min(np.diff(x_lines)); dy_min = min(np.diff(y_lines)); dz_min = min(np.diff(z_lines))
+print(f"[mesh] min steps (mm): dx={dx_min:.3f}, dy={dy_min:.3f}, dz={dz_min:.3f}")

 # Optional smoothing to limit max cell size
 mesh.SmoothMeshLines('all', mesh_res, ratio=1.4)
@@ -146,8 +147,7 @@ mesh.SmoothMeshLines('all', mesh_res, ratio=1.4)
 # MATERIALS & SOLIDS
 # =================
 pec     = CSX.AddMetal('PEC')
-quartzM = CSX.AddMaterial('QUARTZ')
-quartzM.SetMaterialProperty(epsilon=er_quartz)
+quartzM = CSX.AddMaterial('QUARTZ'); quartzM.SetMaterialProperty(epsilon=er_quartz)
 airM    = CSX.AddMaterial('AIR')

 # Quartz full block
@@ -157,12 +157,10 @@ quartzM.AddBox([0, 0, 0], [a, b, guide_length_mm])
 pec.AddBox([-t_metal, 0, 0],     [0,        b,       guide_length_mm])        # left
 pec.AddBox([a,        0, 0],     [a+t_metal,b,       guide_length_mm])        # right
 pec.AddBox([-t_metal,-t_metal,0],[a+t_metal,0,       guide_length_mm])        # bottom
-pec.AddBox(
-    [-t_metal, b, 0], [a + t_metal, b + t_metal, guide_length_mm]
-)  # top (slots will pierce)
+pec.AddBox([-t_metal, b, 0],     [a+t_metal,b+t_metal,guide_length_mm])       # top (slots will pierce)

 # Slots (AIR) overriding top metal
-for zc, xc in zip(z_centers, x_centers, strict=False):
+for zc, xc in zip(z_centers, x_centers):
    x1, x2 = xc - slot_w/2.0, xc + slot_w/2.0
    z1, z2 = zc - slot_L/2.0, zc + slot_L/2.0
    prim = airM.AddBox([x1, b, z1], [x2, b+t_metal, z2])
@@ -212,20 +210,23 @@ if VIEW_GEOM and HAVE_APP and AppCSXCAD_BIN:
 t0 = time.time()
 FDTD.Run(Sim_Path, cleanup=True, verbose=2, numThreads=THREADS)
 t1 = time.time()
+print(f"[timing] FDTD solve elapsed: {t1 - t0:.2f} s")

 # ... right before NF2FF (far-field):
 t2 = time.time()
 try:
-    res = nf2ff.CalcNF2FF(Sim_Path, [f0], theta, phi)  # noqa: F821
-except AttributeError:
-    res = FDTD.CalcNF2FF(nf2ff, Sim_Path, [f0], theta, phi)  # noqa: F821
+    res = nf2ff.CalcNF2FF(Sim_Path, [f0], theta, phi)
+except AttributeError:
+    res = FDTD.CalcNF2FF(nf2ff, Sim_Path, [f0], theta, phi)
 t3 = time.time()
+print(f"[timing] NF2FF (far-field) elapsed: {t3 - t2:.2f} s")

 # ... S-parameters postproc timing (optional):
 t4 = time.time()
-for p in ports:  # noqa: F821
-    p.CalcPort(Sim_Path, freq)  # noqa: F821
+for p in ports:
+    p.CalcPort(Sim_Path, freq)
 t5 = time.time()
+print(f"[timing] Port/S-params postproc elapsed: {t5 - t4:.2f} s")


 # =======
@@ -234,8 +235,11 @@ t5 = time.time()
 if SIMULATE:
    FDTD.Run(Sim_Path, cleanup=True, verbose=2, numThreads=THREADS)

-freq = np.linspace(f_start, f_stop, profiles[PROFILE]["freq_pts"])
-ports = list(FDTD.ports)   # Port 1 & 2 in creation order
+# ==========================
+# POST: S-PARAMS / IMPEDANCE
+# ==========================
+freq = np.linspace(f_start, f_stop, profiles[PROFILE]["freq_pts"])
+ports = [p for p in FDTD.ports]   # Port 1 & 2 in creation order
 for p in ports:
    p.CalcPort(Sim_Path, freq)

@@ -246,19 +250,13 @@ Zin = ports[0].uf_tot / ports[0].if_tot
 plt.figure(figsize=(7.6,4.6))
 plt.plot(freq*1e-9, 20*np.log10(np.abs(S11)), lw=2, label='|S11|')
 plt.plot(freq*1e-9, 20*np.log10(np.abs(S21)), lw=2, ls='--', label='|S21|')
-plt.grid(True)
-plt.legend()
-plt.xlabel('Frequency (GHz)')
-plt.ylabel('Magnitude (dB)')
+plt.grid(True); plt.legend(); plt.xlabel('Frequency (GHz)'); plt.ylabel('Magnitude (dB)')
 plt.title(f'S-Parameters (profile: {PROFILE})')

 plt.figure(figsize=(7.6,4.6))
 plt.plot(freq*1e-9, np.real(Zin), lw=2, label='Re{Zin}')
 plt.plot(freq*1e-9, np.imag(Zin), lw=2, ls='--', label='Im{Zin}')
-plt.grid(True)
-plt.legend()
-plt.xlabel('Frequency (GHz)')
-plt.ylabel('Ohms')
+plt.grid(True); plt.legend(); plt.xlabel('Frequency (GHz)'); plt.ylabel('Ohms')
 plt.title('Input Impedance (Port 1)')

 # ==========================
@@ -279,6 +277,9 @@ mismatch = 1.0 - np.abs(S11[idx_f0])**2
 Gmax_lin = Dmax_lin * float(mismatch)
 Gmax_dBi = 10*np.log10(Gmax_lin)

+print(f"[far-field] Dmax @ {f0/1e9:.3f} GHz: {10*np.log10(Dmax_lin):.2f} dBi")
+print(f"[far-field] mismatch (1-|S11|^2): {float(mismatch):.3f}")
+print(f"[far-field] est. max realized gain: {Gmax_dBi:.2f} dBi")

 # Normalized 3D pattern
 E = np.squeeze(res.E_norm)     # [th, ph]
@@ -294,35 +295,22 @@ ax = fig.add_subplot(111, projection='3d')
 ax.plot_surface(X, Y, Z, rstride=2, cstride=2, linewidth=0, antialiased=True, alpha=0.92)
 ax.set_title(f'Normalized 3D Pattern @ {f0/1e9:.2f} GHz\n(peak ≈ {Gmax_dBi:.1f} dBi)')
 ax.set_box_aspect((1,1,1))
-ax.set_xlabel('x')
-ax.set_ylabel('y')
-ax.set_zlabel('z')
+ax.set_xlabel('x'); ax.set_ylabel('y'); ax.set_zlabel('z')
 plt.tight_layout()

 # ==========================
 # QUICK 2D GEOMETRY PREVIEW
 # ==========================
 plt.figure(figsize=(8.4,2.8))
-plt.fill_between(
-    [0, a],
-    [0, 0],
-    [guide_length_mm, guide_length_mm],
-    color='#dddddd',
-    alpha=0.5,
-    step='pre',
-    label='WG top aperture',
-)
-for zc, xc in zip(z_centers, x_centers, strict=False):
+plt.fill_between([0,a], [0,0], [guide_length_mm, guide_length_mm], color='#dddddd', alpha=0.5, step='pre', label='WG top aperture')
+for zc, xc in zip(z_centers, x_centers):
    plt.gca().add_patch(plt.Rectangle((xc - slot_w/2.0, zc - slot_L/2.0),
                                      slot_w, slot_L, fc='#3355ff', ec='k'))
-plt.xlim(-2, a + 2)
-plt.ylim(-5, guide_length_mm + 5)
+plt.xlim(-2, a+2); plt.ylim(-5, guide_length_mm+5)
 plt.gca().invert_yaxis()
-plt.xlabel('x (mm)')
-plt.ylabel('z (mm)')
+plt.xlabel('x (mm)'); plt.ylabel('z (mm)')
 plt.title(f'Top-view slot layout (N={Nslots}, profile={PROFILE})')
-plt.grid(True)
-plt.legend()
+plt.grid(True); plt.legend()



@@ -68,8 +68,11 @@ def generate_multi_ramp_csv(Fs=125e6, Tb=1e-6, Tau=2e-6, fmax=30e6, fmin=10e6,
    # --- Save CSV (no header)
    df = pd.DataFrame({"time(s)": t_csv, "voltage(V)": y_csv})
    df.to_csv(filename, index=False, header=False)
+    print(f"CSV saved: {filename}")
+    print(f"Total raw samples: {total_samples} | Ramps inserted: {ramps_inserted} | CSV points: {len(y_csv)}")

-    if show_plot or save_plot_png:
+    # --- Plot (staircase)
+    if show_plot or save_plot_png:
        # Choose plotting vectors (use raw DAC samples to keep lines crisp)
        t_plot = t
        y_plot = y
@@ -105,6 +108,7 @@ def generate_multi_ramp_csv(Fs=125e6, Tb=1e-6, Tau=2e-6, fmax=30e6, fmin=10e6,

        if save_plot_png:
            plt.savefig(save_plot_png, dpi=150)
+            print(f"Plot saved: {save_plot_png}")
        if show_plot:
            plt.show()
        else:
@@ -1,6 +1,7 @@
 import matplotlib.pyplot as plt

-line_width = 0.204
+# Dimensions (all in mm)
+line_width = 0.204
 substrate_height = 0.102
 via_drill = 0.20
 via_pad_A = 0.20  # minimal pad case
@@ -26,20 +27,10 @@ ax.axhline(polygon_y2, color="blue", linestyle="--")
 via_positions = [2, 4, 6, 8]  # x positions for visualization
 for x in via_positions:
    # Case A
-    ax.add_patch(
-        plt.Circle(
-            (x, polygon_y1), via_pad_A / 2, facecolor="green", alpha=0.5,
-            label="Via pad A" if x == 2 else ""
-        )
-    )
+    ax.add_patch(plt.Circle((x, polygon_y1), via_pad_A/2, facecolor="green", alpha=0.5, label="Via pad A" if x==2 else ""))
    ax.add_patch(plt.Circle((x, polygon_y2), via_pad_A/2, facecolor="green", alpha=0.5))
    # Case B
-    ax.add_patch(
-        plt.Circle(
-            (-x, polygon_y1), via_pad_B / 2, facecolor="red", alpha=0.3,
-            label="Via pad B" if x == 2 else ""
-        )
-    )
+    ax.add_patch(plt.Circle((-x, polygon_y1), via_pad_B/2, facecolor="red", alpha=0.3, label="Via pad B" if x==2 else ""))
    ax.add_patch(plt.Circle((-x, polygon_y2), via_pad_B/2, facecolor="red", alpha=0.3))

 # Add dimensions text
@@ -1,6 +1,7 @@
 import matplotlib.pyplot as plt

-line_width = 0.204
+# Dimensions (all in mm)
+line_width = 0.204
 via_pad_A = 0.20
 via_pad_B = 0.45
 polygon_offset = 0.30
@@ -25,20 +26,10 @@ ax.axhline(polygon_y2, color="blue", linestyle="--")
 via_positions = [2, 2 + via_pitch]  # two vias for showing spacing
 for x in via_positions:
    # Case A
-    ax.add_patch(
-        plt.Circle(
-            (x, polygon_y1), via_pad_A / 2, facecolor="green", alpha=0.5,
-            label="Via pad A" if x == 2 else ""
-        )
-    )
+    ax.add_patch(plt.Circle((x, polygon_y1), via_pad_A/2, facecolor="green", alpha=0.5, label="Via pad A" if x==2 else ""))
    ax.add_patch(plt.Circle((x, polygon_y2), via_pad_A/2, facecolor="green", alpha=0.5))
    # Case B
-    ax.add_patch(
-        plt.Circle(
-            (-x, polygon_y1), via_pad_B / 2, facecolor="red", alpha=0.3,
-            label="Via pad B" if x == 2 else ""
-        )
-    )
+    ax.add_patch(plt.Circle((-x, polygon_y1), via_pad_B/2, facecolor="red", alpha=0.3, label="Via pad B" if x==2 else ""))
    ax.add_patch(plt.Circle((-x, polygon_y2), via_pad_B/2, facecolor="red", alpha=0.3))

 # Add text annotations
@@ -49,17 +40,15 @@ ax.text(-2, polygon_y1 + 0.5, "Via B Ø0.45 mm pad", color="red")

 # Add pitch dimension (horizontal between vias)
 ax.annotate("", xy=(2, polygon_y1 + 0.2), xytext=(2 + via_pitch, polygon_y1 + 0.2),
-            arrowprops={"arrowstyle": "<->", "color": "purple"})
+            arrowprops=dict(arrowstyle="<->", color="purple"))
 ax.text(2 + via_pitch/2, polygon_y1 + 0.3, f"{via_pitch:.2f} mm pitch", color="purple", ha="center")

 # Add distance from RF line edge to via center
 line_edge_y = rf_line_y + line_width/2
 via_center_y = polygon_y1
 ax.annotate("", xy=(2.4, line_edge_y), xytext=(2.4, via_center_y),
-            arrowprops={"arrowstyle": "<->", "color": "brown"})
-ax.text(
-    2.5, (line_edge_y + via_center_y) / 2, f"{via_center_offset:.2f} mm", color="brown", va="center"
-)
+            arrowprops=dict(arrowstyle="<->", color="brown"))
+ax.text(2.5, (line_edge_y + via_center_y)/2, f"{via_center_offset:.2f} mm", color="brown", va="center")

 # Formatting
 ax.set_xlim(-5, 5)
@@ -27,7 +27,7 @@ n_idx = np.arange(N) - (N-1)/2
 y_positions = m_idx * dy
 z_positions = n_idx * dz

-def element_factor(theta_rad, _phi_rad):
+def element_factor(theta_rad, phi_rad):
    return np.abs(np.cos(theta_rad))

 def array_factor(theta_rad, phi_rad, y_positions, z_positions, wy, wz, theta0_rad, phi0_rad):
@@ -105,3 +105,5 @@ plt.title('Array Pattern Heatmap (|AF·EF|, dB) — Kaiser ~-25 dB')
 plt.tight_layout()
 plt.savefig('Heatmap_Kaiser25dB_like.png', bbox_inches='tight')
 plt.show()
+
+print('Saved: E_plane_Kaiser25dB_like.png, H_plane_Kaiser25dB_like.png, Heatmap_Kaiser25dB_like.png')
@@ -15,20 +15,12 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
    timestamp_ns = 0
    
    # Target parameters
-    targets = [
-        {
-            'range': 3000, 'velocity': 25, 'snr': 30, 'azimuth': 10, 'elevation': 5
-        },  # Fast moving target
-        {
-            'range': 5000, 'velocity': -15, 'snr': 25, 'azimuth': 20, 'elevation': 2
-        },  # Approaching target
-        {
-            'range': 8000, 'velocity': 5, 'snr': 20, 'azimuth': 30, 'elevation': 8
-        },  # Slow moving target
-        {
-            'range': 12000, 'velocity': -8, 'snr': 18, 'azimuth': 45, 'elevation': 3
-        },  # Distant target
-    ]
+    targets = [
+        {'range': 3000, 'velocity': 25, 'snr': 30, 'azimuth': 10, 'elevation': 5},   # Fast moving target
+        {'range': 5000, 'velocity': -15, 'snr': 25, 'azimuth': 20, 'elevation': 2},  # Approaching target
+        {'range': 8000, 'velocity': 5, 'snr': 20, 'azimuth': 30, 'elevation': 8},    # Slow moving target
+        {'range': 12000, 'velocity': -8, 'snr': 18, 'azimuth': 45, 'elevation': 3},  # Distant target
+    ]
    
    # Noise parameters
    noise_std = 5
@@ -38,6 +30,7 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
    chirp_number = 0
    
    # Generate Long Chirps (30µs duration equivalent)
+    print("Generating Long Chirps...")
    for chirp in range(num_long_chirps):
        for sample in range(samples_per_chirp):
            # Base noise
@@ -45,7 +38,7 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
            q_val = np.random.normal(0, noise_std)
            
            # Add clutter (stationary targets)
-            _clutter_range = 2000  # Fixed clutter at 2km
+            clutter_range = 2000  # Fixed clutter at 2km
            if sample < 100:  # Simulate clutter in first 100 samples
                i_val += np.random.normal(0, clutter_std)
                q_val += np.random.normal(0, clutter_std)
@@ -54,9 +47,7 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
            for target in targets:
                # Calculate range bin (simplified)
                range_bin = int(target['range'] / 20)  # ~20m per bin
-                doppler_phase = (
-                    2 * math.pi * target['velocity'] * chirp / 100
-                )  # Doppler phase shift
+                doppler_phase = 2 * math.pi * target['velocity'] * chirp / 100  # Doppler phase shift
                
                # Target appears around its range bin with some spread
                if abs(sample - range_bin) < 10:
@@ -89,6 +80,7 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
    timestamp_ns += 175400  # 175.4µs guard time
    
    # Generate Short Chirps (0.5µs duration equivalent)
+    print("Generating Short Chirps...")
    for chirp in range(num_short_chirps):
        for sample in range(samples_per_chirp):
            # Base noise
@@ -104,9 +96,7 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
            for target in targets:
                # Range bin calculation (different for short chirps)
                range_bin = int(target['range'] / 40)  # Different range resolution
-                doppler_phase = (
-                    2 * math.pi * target['velocity'] * (chirp + 5) / 80
-                )  # Different Doppler
+                doppler_phase = 2 * math.pi * target['velocity'] * (chirp + 5) / 80  # Different Doppler
                
                # Target appears around its range bin
                if abs(sample - range_bin) < 8:
@@ -140,6 +130,11 @@ def generate_radar_csv(filename="pulse_compression_output.csv"):
    
    # Save to CSV
    df.to_csv(filename, index=False)
+    print(f"Generated CSV file: {filename}")
+    print(f"Total samples: {len(df)}")
+    print(f"Long chirps: {num_long_chirps}, Short chirps: {num_short_chirps}")
+    print(f"Samples per chirp: {samples_per_chirp}")
+    print(f"File size: {len(df) // 1000}K samples")
    
    return df

@@ -147,11 +142,15 @@ def analyze_generated_data(df):
    """
    Analyze the generated data to verify target detection
    """
+    print("\n=== Data Analysis ===")
    
    # Basic statistics
-    df[df['chirp_type'] == 'LONG']
-    df[df['chirp_type'] == 'SHORT']
+    long_chirps = df[df['chirp_type'] == 'LONG']
+    short_chirps = df[df['chirp_type'] == 'SHORT']
    
+    print(f"Long chirp samples: {len(long_chirps)}")
+    print(f"Short chirp samples: {len(short_chirps)}")
+    print(f"Unique chirp numbers: {df['chirp_number'].nunique()}")
    
    # Calculate actual magnitude and phase for analysis
    df['magnitude'] = np.sqrt(df['I_value']**2 + df['Q_value']**2)
@@ -161,11 +160,15 @@ def analyze_generated_data(df):
    high_mag_threshold = df['magnitude'].quantile(0.95)  # Top 5%
    targets_detected = df[df['magnitude'] > high_mag_threshold]
    
+    print(f"\nTarget detection threshold: {high_mag_threshold:.2f}")
+    print(f"High magnitude samples: {len(targets_detected)}")
    
    # Group by chirp type
-    targets_detected[targets_detected['chirp_type'] == 'LONG']
-    targets_detected[targets_detected['chirp_type'] == 'SHORT']
+    long_targets = targets_detected[targets_detected['chirp_type'] == 'LONG']
+    short_targets = targets_detected[targets_detected['chirp_type'] == 'SHORT']
    
+    print(f"Targets in long chirps: {len(long_targets)}")
+    print(f"Targets in short chirps: {len(short_targets)}")
    
    return df

@@ -176,3 +179,10 @@ if __name__ == "__main__":
    # Analyze the generated data
    analyze_generated_data(df)
    
+    print("\n=== CSV File Ready ===")
+    print("You can now test the Python GUI with this CSV file!")
+    print("The file contains:")
+    print("- 16 Long chirps + 16 Short chirps")
+    print("- 4 simulated targets at different ranges and velocities")
+    print("- Realistic noise and clutter")
+    print("- Proper I/Q data for Doppler processing")
@@ -90,6 +90,8 @@ def generate_small_radar_csv(filename="small_test_radar_data.csv"):
    
    df = pd.DataFrame(data)
    df.to_csv(filename, index=False)
+    print(f"Generated small CSV: {filename}")
+    print(f"Total samples: {len(df)}")
    return df

 generate_small_radar_csv()
@@ -1,5 +1,5 @@
 import numpy as np
-from numpy.fft import fft
+from numpy.fft import fft, ifft
 import matplotlib.pyplot as plt


@@ -15,10 +15,7 @@ theta_n= 2*np.pi*(pow(N,2)*pow(Ts,2)*(fmax-fmin)/(2*Tb)+fmin*N*Ts) # instantaneo
 y = 1 + np.sin(theta_n) # ramp signal in time domain

 M = np.arange(n, 2*n, 1)
-theta_m= (
-    2*np.pi*(pow(M,2)*pow(Ts,2)*(-fmax+fmin)/(2*Tb)+(-fmin+2*fmax)*M*Ts)
-    - 2*np.pi*((fmin-fmax)*Tb/2+(2*fmax-fmin)*Tb)
-) # instantaneous phase
+theta_m= 2*np.pi*(pow(M,2)*pow(Ts,2)*(-fmax+fmin)/(2*Tb)+(-fmin+2*fmax)*M*Ts)-2*np.pi*((fmin-fmax)*Tb/2+(2*fmax-fmin)*Tb) # instantaneous phase
 z = 1 + np.sin(theta_m) # ramp signal in time domain

 x = np.concatenate((y, z))
@@ -26,9 +23,9 @@ x = np.concatenate((y, z))
 t = Ts*np.arange(0,2*n,1)
 X = fft(x)
 L =len(X)
-freq_indices = np.arange(L)
+l = np.arange(L)
 T = L*Ts
-freq = freq_indices/T
+freq = l/T


 plt.figure(figsize = (12, 6))
@@ -15,10 +15,7 @@ theta_n= 2*np.pi*(pow(N,2)*pow(Ts,2)*(fmax-fmin)/(2*Tb)+fmin*N*Ts) # instantaneo
 y = 1 + np.sin(theta_n) # ramp signal in time domain

 M = np.arange(n, 2*n, 1)
-theta_m= (
-    2*np.pi*(pow(M,2)*pow(Ts,2)*(-fmax+fmin)/(2*Tb)+(-fmin+2*fmax)*M*Ts)
-    - 2*np.pi*((fmin-fmax)*Tb/2+(2*fmax-fmin)*Tb)
-) # instantaneous phase
+theta_m= 2*np.pi*(pow(M,2)*pow(Ts,2)*(-fmax+fmin)/(2*Tb)+(-fmin+2*fmax)*M*Ts)-2*np.pi*((fmin-fmax)*Tb/2+(2*fmax-fmin)*Tb) # instantaneous phase
 z = 1 + np.sin(theta_m) # ramp signal in time domain

 x = np.concatenate((y, z))
@@ -27,10 +24,11 @@ t = Ts*np.arange(0,2*n,1)
 plt.plot(t, x)
 X = fft(x)
 L =len(X)
-freq_indices = np.arange(L)
+l = np.arange(L)
 T = L*Ts
-freq = freq_indices/T
+freq = l/T

+print("The Array is: ", x) #printing the array

 plt.figure(figsize = (12, 6))
 plt.subplot(121)
@@ -1,10 +1,7 @@
 import numpy as np

 # Define parameters
-# NOTE: This is a standalone LUT generation utility. The production chirp LUT
-# is generated by 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py with
-# CHIRP_BW=20e6 (target: 30e6 Phase 1) and DAC_CLK=120e6.
-fs = 120e6  # Sampling frequency (DAC clock from AD9523 OUT10)
+fs = 120e6  # Sampling frequency
 Ts = 1 / fs  # Sampling time
 Tb = 1e-6  # Burst time
 Tau = 30e-6  # Pulse repetition time
@@ -23,5 +20,5 @@ y = 1 + np.sin(theta_n)  # Normalize from 0 to 2
 y_scaled = np.round(y * 127.5).astype(int)  # Scale to 8-bit range (0-255)

 # Print values in Verilog-friendly format
-for _i in range(n):
-    pass
+for i in range(n):
+    print(f"waveform_LUT[{i}] = 8'h{y_scaled[i]:02X};")
@@ -58,10 +58,10 @@ class RadarCalculatorGUI:
        scrollbar = ttk.Scrollbar(self.input_frame, orient="vertical", command=canvas.yview)
        scrollable_frame = ttk.Frame(canvas)
        
-        scrollable_frame.bind(
-            "<Configure>",
-            lambda _e: canvas.configure(scrollregion=canvas.bbox("all"))
-        )
+        scrollable_frame.bind(
+            "<Configure>",
+            lambda e: canvas.configure(scrollregion=canvas.bbox("all"))
+        )
        
        canvas.create_window((0, 0), window=scrollable_frame, anchor="nw")
        canvas.configure(yscrollcommand=scrollbar.set)
@@ -83,7 +83,7 @@ class RadarCalculatorGUI:
        
        self.entries = {}
        
-        for _i, (label, default) in enumerate(inputs):
+        for i, (label, default) in enumerate(inputs):
            # Create a frame for each input row
            row_frame = ttk.Frame(scrollable_frame)
            row_frame.pack(fill=tk.X, pady=5)
@@ -119,8 +119,8 @@ class RadarCalculatorGUI:
        calculate_btn.pack()
        
        # Bind hover effect
-        calculate_btn.bind("<Enter>", lambda _e: calculate_btn.config(bg='#45a049'))
-        calculate_btn.bind("<Leave>", lambda _e: calculate_btn.config(bg='#4CAF50'))
+        calculate_btn.bind("<Enter>", lambda e: calculate_btn.config(bg='#45a049'))
+        calculate_btn.bind("<Leave>", lambda e: calculate_btn.config(bg='#4CAF50'))
        
    def create_results_display(self):
        """Create the results display area"""
@@ -135,10 +135,10 @@ class RadarCalculatorGUI:
        scrollbar = ttk.Scrollbar(self.results_frame, orient="vertical", command=canvas.yview)
        scrollable_frame = ttk.Frame(canvas)
        
-        scrollable_frame.bind(
-            "<Configure>",
-            lambda _e: canvas.configure(scrollregion=canvas.bbox("all"))
-        )
+        scrollable_frame.bind(
+            "<Configure>",
+            lambda e: canvas.configure(scrollregion=canvas.bbox("all"))
+        )
        
        canvas.create_window((0, 0), window=scrollable_frame, anchor="nw")
        canvas.configure(yscrollcommand=scrollbar.set)
@@ -158,7 +158,7 @@ class RadarCalculatorGUI:
        
        self.results_labels = {}
        
-        for _i, (label, key) in enumerate(results):
+        for i, (label, key) in enumerate(results):
            # Create a frame for each result row
            row_frame = ttk.Frame(scrollable_frame)
            row_frame.pack(fill=tk.X, pady=10, padx=20)
@@ -180,10 +180,10 @@ class RadarCalculatorGUI:
        note_text = """
        NOTES:
        • Maximum detectable range is calculated using the radar equation
-        • Range resolution = c x τ / 2, where τ is pulse duration
-        • Maximum unambiguous range = c / (2 x PRF)
-        • Maximum detectable speed = λ x PRF / 4
-        • Speed resolution = λ x PRF / (2 x N) where N is number of pulses (assumed 1)
+        • Range resolution = c × τ / 2, where τ is pulse duration
+        • Maximum unambiguous range = c / (2 × PRF)
+        • Maximum detectable speed = λ × PRF / 4
+        • Speed resolution = λ × PRF / (2 × N) where N is number of pulses (assumed 1)
        • λ (wavelength) = c / f
        """
        
@@ -221,10 +221,7 @@ class RadarCalculatorGUI:
            temp = self.get_float_value(self.entries["Temperature (K):"])
            
            # Validate inputs
-            if None in [
-                f_ghz, pulse_duration_us, prf, p_dbm, g_dbi,
-                sens_dbm, rcs, losses_db, nf_db, temp,
-            ]:
+            if None in [f_ghz, pulse_duration_us, prf, p_dbm, g_dbi, sens_dbm, rcs, losses_db, nf_db, temp]:
                messagebox.showerror("Error", "Please enter valid numeric values for all fields")
                return
                
@@ -238,7 +235,7 @@ class RadarCalculatorGUI:
            g_linear = 10 ** (g_dbi / 10)
            sens_linear = 10 ** ((sens_dbm - 30) / 10)
            losses_linear = 10 ** (losses_db / 10)
-            _nf_linear = 10 ** (nf_db / 10)
+            nf_linear = 10 ** (nf_db / 10)
            
            # Calculate receiver noise power
            if k is None:
@@ -300,15 +297,12 @@ class RadarCalculatorGUI:
            # Show success message
            messagebox.showinfo("Success", "Calculation completed successfully!")
            
-        except (ValueError, ZeroDivisionError) as e:
-            messagebox.showerror(
-                "Calculation Error",
-                f"An error occurred during calculation:\n{e!s}",
-            )
+        except Exception as e:
+            messagebox.showerror("Calculation Error", f"An error occurred during calculation:\n{str(e)}")
            
 def main():
    root = tk.Tk()
-    _app = RadarCalculatorGUI(root)
+    app = RadarCalculatorGUI(root)
    root.mainloop()

 if __name__ == "__main__":
@@ -12,22 +12,13 @@ def calculate_patch_antenna_parameters(frequency, epsilon_r, h_sub, h_cu, array)
    lamb = c /(frequency * 1e9)
    
    # Calculate the effective dielectric constant
-    epsilon_eff = (
-        (epsilon_r + 1) / 2
-        + (epsilon_r - 1) / 2 * (1 + 12 * h_sub_m / (array[1] * h_cu_m)) ** (-0.5)
-    )
+    epsilon_eff = (epsilon_r + 1) / 2 + (epsilon_r - 1) / 2 * (1 + 12 * h_sub_m / (array[1] * h_cu_m)) ** (-0.5)
    
    # Calculate the width of the patch
    W = c / (2 * frequency * 1e9) * np.sqrt(2 / (epsilon_r + 1))
    
    # Calculate the effective length
-    delta_L = (
-        0.412
-        * h_sub_m
-        * (epsilon_eff + 0.3)
-        * (W / h_sub_m + 0.264)
-        / ((epsilon_eff - 0.258) * (W / h_sub_m + 0.8))
-    )
+    delta_L = 0.412 * h_sub_m * (epsilon_eff + 0.3) * (W / h_sub_m + 0.264) / ((epsilon_eff - 0.258) * (W / h_sub_m + 0.8))
    
    # Calculate the length of the patch
    L = c / (2 * frequency * 1e9 * np.sqrt(epsilon_eff)) - 2 * delta_L
@@ -40,10 +31,7 @@ def calculate_patch_antenna_parameters(frequency, epsilon_r, h_sub, h_cu, array)
    
    # Calculate the feeding line width (W_feed)
    Z0 = 50  # Characteristic impedance of the feeding line (typically 50 ohms)
-    A = (
-        Z0 / 60 * np.sqrt((epsilon_r + 1) / 2)
-        + (epsilon_r - 1) / (epsilon_r + 1) * (0.23 + 0.11 / epsilon_r)
-    )
+    A = Z0 / 60 * np.sqrt((epsilon_r + 1) / 2) + (epsilon_r - 1) / (epsilon_r + 1) * (0.23 + 0.11 / epsilon_r)
    W_feed = 8 * h_sub_m / np.exp(A) - 2 * h_cu_m
    
    # Convert results back to mm
@@ -62,7 +50,10 @@ h_sub = 0.102  # Height of substrate in mm
 h_cu = 0.07  # Height of copper in mm
 array = [2, 2]  # 2x2 array

-W_mm, L_mm, dx_mm, dy_mm, W_feed_mm = calculate_patch_antenna_parameters(
-    frequency, epsilon_r, h_sub, h_cu, array
-)
+W_mm, L_mm, dx_mm, dy_mm, W_feed_mm = calculate_patch_antenna_parameters(frequency, epsilon_r, h_sub, h_cu, array)

+print(f"Width of the patch: {W_mm:.4f} mm")
+print(f"Length of the patch: {L_mm:.4f} mm")
+print(f"Separation distance in horizontal axis: {dx_mm:.4f} mm")
+print(f"Separation distance in vertical axis: {dy_mm:.4f} mm")
+print(f"Feeding line width: {W_feed_mm:.2f} mm")
@@ -1,116 +0,0 @@
-// ADAR1000_AGC.cpp -- STM32 outer-loop AGC implementation
-//
-// See ADAR1000_AGC.h for architecture overview.
-
-#include "ADAR1000_AGC.h"
-#include "ADAR1000_Manager.h"
-#include "diag_log.h"
-
-#include <cstring>
-
-// ---------------------------------------------------------------------------
-// Constructor -- set all config fields to safe defaults
-// ---------------------------------------------------------------------------
-ADAR1000_AGC::ADAR1000_AGC()
-    : agc_base_gain(ADAR1000Manager::kDefaultRxVgaGain) // 30
-    , gain_step_down(4)
-    , gain_step_up(1)
-    , min_gain(0)
-    , max_gain(127)
-    , holdoff_frames(4)
-    , enabled(true)
-    , holdoff_counter(0)
-    , last_saturated(false)
-    , saturation_event_count(0)
-{
-    memset(cal_offset, 0, sizeof(cal_offset));
-}
-
-// ---------------------------------------------------------------------------
-// update -- called once per frame with the FPGA DIG_5 saturation flag
-//
-// Returns true if agc_base_gain changed (caller should then applyGain).
-// ---------------------------------------------------------------------------
-void ADAR1000_AGC::update(bool fpga_saturation)
-{
-    if (!enabled)
-        return;
-
-    last_saturated = fpga_saturation;
-
-    if (fpga_saturation) {
-        // Attack: reduce gain immediately
-        saturation_event_count++;
-        holdoff_counter = 0;
-
-        if (agc_base_gain >= gain_step_down + min_gain) {
-            agc_base_gain -= gain_step_down;
-        } else {
-            agc_base_gain = min_gain;
-        }
-
-        DIAG("AGC", "SAT detected -- gain_base -> %u  (events=%lu)",
-             (unsigned)agc_base_gain, (unsigned long)saturation_event_count);
-
-    } else {
-        // Recovery: wait for holdoff, then increase gain
-        holdoff_counter++;
-
-        if (holdoff_counter >= holdoff_frames) {
-            holdoff_counter = 0;
-
-            if (agc_base_gain + gain_step_up <= max_gain) {
-                agc_base_gain += gain_step_up;
-            } else {
-                agc_base_gain = max_gain;
-            }
-
-            DIAG("AGC", "Recovery step -- gain_base -> %u", (unsigned)agc_base_gain);
-        }
-    }
-}
-
-// ---------------------------------------------------------------------------
-// applyGain -- write effective gain to all 16 RX VGA channels
-//
-// Uses the Manager's adarSetRxVgaGain which takes 1-based channel indices
-// (matching the convention in setBeamAngle).
-// ---------------------------------------------------------------------------
-void ADAR1000_AGC::applyGain(ADAR1000Manager &mgr)
-{
-    for (uint8_t dev = 0; dev < AGC_NUM_DEVICES; ++dev) {
-        for (uint8_t ch = 0; ch < AGC_NUM_CHANNELS; ++ch) {
-            uint8_t gain = effectiveGain(dev * AGC_NUM_CHANNELS + ch);
-            // Channel parameter is 1-based per Manager convention
-            mgr.adarSetRxVgaGain(dev, ch + 1, gain, BROADCAST_OFF);
-        }
-    }
-}
-
-// ---------------------------------------------------------------------------
-// resetState -- clear runtime counters, preserve configuration
-// ---------------------------------------------------------------------------
-void ADAR1000_AGC::resetState()
-{
-    holdoff_counter = 0;
-    last_saturated = false;
-    saturation_event_count = 0;
-}
-
-// ---------------------------------------------------------------------------
-// effectiveGain -- compute clamped per-channel gain
-// ---------------------------------------------------------------------------
-uint8_t ADAR1000_AGC::effectiveGain(uint8_t channel_index) const
-{
-    if (channel_index >= AGC_TOTAL_CHANNELS)
-        return min_gain;  // safety fallback — OOB channels get minimum gain
-
-    int16_t raw = static_cast<int16_t>(agc_base_gain) + cal_offset[channel_index];
-
-    if (raw < static_cast<int16_t>(min_gain))
-        return min_gain;
-    if (raw > static_cast<int16_t>(max_gain))
-        return max_gain;
-
-    return static_cast<uint8_t>(raw);
-}
@@ -1,97 +0,0 @@
-// ADAR1000_AGC.h -- STM32 outer-loop AGC for ADAR1000 RX VGA gain
-//
-// Adjusts the analog VGA common-mode gain on each ADAR1000 RX channel based on
-// the FPGA's saturation flag (DIG_5 / PD13).  Runs once per radar frame
-// (~258 ms) in the main loop, after runRadarPulseSequence().
-//
-// Architecture:
-//   - Inner loop (FPGA, per-sample): rx_gain_control auto-adjusts digital
-//     gain_shift based on peak magnitude / saturation.  Range ±42 dB.
-//   - Outer loop (THIS MODULE, per-frame): reads FPGA DIG_5 GPIO.  If
-//     saturation detected, reduces agc_base_gain immediately (attack).  If no
-//     saturation for holdoff_frames, increases agc_base_gain (decay/recovery).
-//
-// Per-channel gain formula:
-//   VGA[dev][ch] = clamp(agc_base_gain + cal_offset[dev*4+ch], min_gain, max_gain)
-//
-// The cal_offset array allows per-element calibration to correct inter-channel
-// gain imbalance.  Default is all zeros (uniform gain).
-
-#ifndef ADAR1000_AGC_H
-#define ADAR1000_AGC_H
-
-#include <stdint.h>
-
-// Forward-declare to avoid pulling in the full ADAR1000_Manager header here.
-// The .cpp includes the real header.
-class ADAR1000Manager;
-
-// Number of ADAR1000 devices
-#define AGC_NUM_DEVICES   4
-// Number of channels per ADAR1000
-#define AGC_NUM_CHANNELS  4
-// Total RX channels
-#define AGC_TOTAL_CHANNELS (AGC_NUM_DEVICES * AGC_NUM_CHANNELS)
-
-class ADAR1000_AGC {
-public:
-    // --- Configuration (public for easy field-testing / GUI override) ---
-
-    // Common-mode base gain (raw ADAR1000 register value, 0-255).
-    // Default matches ADAR1000Manager::kDefaultRxVgaGain = 30.
-    uint8_t agc_base_gain;
-
-    // Per-channel calibration offset (signed, added to agc_base_gain).
-    // Index = device*4 + channel.  Default: all 0.
-    int8_t cal_offset[AGC_TOTAL_CHANNELS];
-
-    // How much to decrease agc_base_gain per frame when saturated (attack).
-    uint8_t gain_step_down;
-
-    // How much to increase agc_base_gain per frame when recovering (decay).
-    uint8_t gain_step_up;
-
-    // Minimum allowed agc_base_gain (floor).
-    uint8_t min_gain;
-
-    // Maximum allowed agc_base_gain (ceiling).
-    uint8_t max_gain;
-
-    // Number of consecutive non-saturated frames required before gain-up.
-    uint8_t holdoff_frames;
-
-    // Master enable.  When false, update() is a no-op.
-    bool enabled;
-
-    // --- Runtime state (read-only for diagnostics) ---
-
-    // Consecutive non-saturated frame counter (resets on saturation).
-    uint8_t holdoff_counter;
-
-    // True if the last update() saw saturation.
-    bool last_saturated;
-
-    // Total saturation events since reset/construction.
-    uint32_t saturation_event_count;
-
-    // --- Methods ---
-
-    ADAR1000_AGC();
-
-    // Call once per frame after runRadarPulseSequence().
-    // fpga_saturation: result of HAL_GPIO_ReadPin(GPIOD, GPIO_PIN_13) == GPIO_PIN_SET
-    void update(bool fpga_saturation);
-
-    // Apply the current gain to all 16 RX VGA channels via the Manager.
-    void applyGain(ADAR1000Manager &mgr);
-
-    // Reset runtime state (holdoff counter, saturation count) without
-    // changing configuration.
-    void resetState();
-
-    // Compute the effective gain for a specific channel index (0-15),
-    // clamped to [min_gain, max_gain].  Useful for diagnostics.
-    uint8_t effectiveGain(uint8_t channel_index) const;
-};
-
-#endif // ADAR1000_AGC_H
@@ -6,23 +6,23 @@ RadarSettings::RadarSettings() {
 }

 void RadarSettings::resetToDefaults() {
-    system_frequency = 10.5e9;    // 10.5 GHz (PLFM TX LO, ADF4382 config)
-    chirp_duration_1 = 30.0e-6;   // 30 µs
-    chirp_duration_2 = 0.5e-6;    // 0.5 µs
+    system_frequency = 10.0e9;    // 10 GHz
+    chirp_duration_1 = 30.0e-6;   // 30 µs
+    chirp_duration_2 = 0.5e-6;    // 0.5 µs
    chirps_per_position = 32;
    freq_min = 10.0e6;           // 10 MHz
    freq_max = 30.0e6;           // 30 MHz
    prf1 = 1000.0;               // 1 kHz
    prf2 = 2000.0;               // 2 kHz
-    max_distance = 1536.0;       // 1536 m (64 bins × 24 m, 3 km mode)
-    map_size = 1536.0;           // 1536 m
+    max_distance = 50000.0;      // 50 km
+    map_size = 50000.0;          // 50 km
    
    settings_valid = true;
 }

 bool RadarSettings::parseFromUSB(const uint8_t* data, uint32_t length) {
-    // Minimum packet size: "SET" + 9 doubles + 1 uint32_t + "END" = 3 + 9*8 + 4 + 3 = 82 bytes
-    if (data == nullptr || length < 82) {
+    // Minimum packet size: "SET" + 8 doubles + 1 uint32_t + "END" = 3 + 8*8 + 4 + 3 = 74 bytes
+    if (data == nullptr || length < 74) {
        settings_valid = false;
        return false;
    }
@@ -88,7 +88,7 @@ bool RadarSettings::validateSettings() {
    if (prf1 < 100 || prf1 > 10000) return false;
    if (prf2 < 100 || prf2 > 10000) return false;
    if (max_distance < 100 || max_distance > 100000) return false;
-    if (map_size < 100 || map_size > 200000) return false;
+    if (map_size < 1000 || map_size > 200000) return false;
    
    return true;
 }
@@ -43,11 +43,6 @@ void USBHandler::processStartFlag(const uint8_t* data, uint32_t length) {
    // Start flag: bytes [23, 46, 158, 237]
    const uint8_t START_FLAG[] = {23, 46, 158, 237};
    
-    // Guard: need at least 4 bytes to contain a start flag.
-    // Without this, length - 4 wraps to ~4 billion (uint32_t unsigned underflow)
-    // and the loop reads far past the buffer boundary.
-    if (length < 4) return;
-    
    // Check if start flag is in the received data
    for (uint32_t i = 0; i <= length - 4; i++) {
        if (memcmp(data + i, START_FLAG, 4) == 0) {
@@ -23,7 +23,6 @@
 #include "usbd_cdc_if.h"
 #include "adar1000.h"
 #include "ADAR1000_Manager.h"
-#include "ADAR1000_AGC.h"
 extern "C" {
 #include "ad9523.h"
 }
@@ -225,7 +224,6 @@ extern SPI_HandleTypeDef hspi4;
 //ADAR1000

 ADAR1000Manager adarManager;
-ADAR1000_AGC    outerAgc;
 static uint8_t matrix1[15][16];
 static uint8_t matrix2[15][16];
 static uint8_t vector_0[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
@@ -641,7 +639,6 @@ SystemError_t checkSystemHealth(void) {
        if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
            current_error = ERROR_AD9523_CLOCK;
            DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
-            return current_error;
        }
        last_clock_check = HAL_GetTick();
    }
@@ -652,12 +649,10 @@ SystemError_t checkSystemHealth(void) {
        if (!tx_locked) {
            current_error = ERROR_ADF4382_TX_UNLOCK;
            DIAG_ERR("LO", "Health check: TX LO UNLOCKED");
-            return current_error;
        }
        if (!rx_locked) {
            current_error = ERROR_ADF4382_RX_UNLOCK;
            DIAG_ERR("LO", "Health check: RX LO UNLOCKED");
-            return current_error;
        }
    }

@@ -666,14 +661,14 @@ SystemError_t checkSystemHealth(void) {
        if (!adarManager.verifyDeviceCommunication(i)) {
            current_error = ERROR_ADAR1000_COMM;
            DIAG_ERR("BF", "Health check: ADAR1000 #%d comm FAILED", i);
-            return current_error;
+            break;
        }

        float temp = adarManager.readTemperature(i);
        if (temp > 85.0f) {
            current_error = ERROR_ADAR1000_TEMP;
            DIAG_ERR("BF", "Health check: ADAR1000 #%d OVERTEMP %.1fC > 85C", i, temp);
-            return current_error;
+            break;
        }
    }

@@ -683,7 +678,6 @@ SystemError_t checkSystemHealth(void) {
        if (!GY85_Update(&imu)) {
            current_error = ERROR_IMU_COMM;
            DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
-            return current_error;
        }
        last_imu_check = HAL_GetTick();
    }
@@ -695,7 +689,6 @@ SystemError_t checkSystemHealth(void) {
        if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
            current_error = ERROR_BMP180_COMM;
            DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
-            return current_error;
        }
        last_bmp_check = HAL_GetTick();
    }
@@ -708,7 +701,6 @@ SystemError_t checkSystemHealth(void) {
    if (HAL_GetTick() - last_gps_fix > 30000) {
        current_error = ERROR_GPS_COMM;
        DIAG_WARN("SYS", "Health check: GPS no fix for >30s");
-        return current_error;
    }

    // 7. Check RF Power Amplifier Current
@@ -717,12 +709,12 @@ SystemError_t checkSystemHealth(void) {
            if (Idq_reading[i] > 2.5f) {
                current_error = ERROR_RF_PA_OVERCURRENT;
                DIAG_ERR("PA", "Health check: PA ch%d OVERCURRENT Idq=%.3fA > 2.5A", i, Idq_reading[i]);
-                return current_error;
+                break;
            }
            if (Idq_reading[i] < 0.1f) {
                current_error = ERROR_RF_PA_BIAS;
                DIAG_ERR("PA", "Health check: PA ch%d BIAS FAULT Idq=%.3fA < 0.1A", i, Idq_reading[i]);
-                return current_error;
+                break;
            }
        }
    }
@@ -731,7 +723,6 @@ SystemError_t checkSystemHealth(void) {
    if (temperature > 75.0f) {
        current_error = ERROR_TEMPERATURE_HIGH;
        DIAG_ERR("SYS", "Health check: System OVERTEMP %.1fC > 75C", temperature);
-        return current_error;
    }

    // 9. Simple watchdog check
@@ -739,7 +730,6 @@ SystemError_t checkSystemHealth(void) {
    if (HAL_GetTick() - last_health_check > 60000) {
        current_error = ERROR_WATCHDOG_TIMEOUT;
        DIAG_ERR("SYS", "Health check: Watchdog timeout (>60s since last check)");
-        return current_error;
    }
    last_health_check = HAL_GetTick();

@@ -929,41 +919,38 @@ bool checkSystemHealthStatus(void) {
 // Get system status for GUI
 // Get system status for GUI with 8 temperature variables
 void getSystemStatusForGUI(char* status_buffer, size_t buffer_size) {
-    // Build status string directly in the output buffer using offset-tracked
-    // snprintf.  Each call returns the number of chars written (excluding NUL),
-    // so we advance 'off' and shrink 'rem' to guarantee we never overflow.
-    size_t off = 0;
-    size_t rem = buffer_size;
-    int w;
+    char temp_buffer[200];
+    char final_status[500] = "System Status: ";

    // Basic status
    if (system_emergency_state) {
-        w = snprintf(status_buffer + off, rem, "System Status: EMERGENCY_STOP|");
+        strcat(final_status, "EMERGENCY_STOP|");
    } else {
-        w = snprintf(status_buffer + off, rem, "System Status: NORMAL|");
+        strcat(final_status, "NORMAL|");
    }
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }

    // Error information
-    w = snprintf(status_buffer + off, rem, "LastError:%d|ErrorCount:%lu|",
-                 last_error, error_count);
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+    snprintf(temp_buffer, sizeof(temp_buffer), "LastError:%d|ErrorCount:%lu|",
+             last_error, error_count);
+    strcat(final_status, temp_buffer);

    // Sensor status
-    w = snprintf(status_buffer + off, rem, "IMU:%.1f,%.1f,%.1f|GPS:%.6f,%.6f|ALT:%.1f|",
-                 Pitch_Sensor, Roll_Sensor, Yaw_Sensor,
-                 RADAR_Latitude, RADAR_Longitude, RADAR_Altitude);
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+    snprintf(temp_buffer, sizeof(temp_buffer), "IMU:%.1f,%.1f,%.1f|GPS:%.6f,%.6f|ALT:%.1f|",
+             Pitch_Sensor, Roll_Sensor, Yaw_Sensor,
+             RADAR_Latitude, RADAR_Longitude, RADAR_Altitude);
+    strcat(final_status, temp_buffer);

    // LO Status
    bool tx_locked, rx_locked;
    ADF4382A_CheckLockStatus(&lo_manager, &tx_locked, &rx_locked);
-    w = snprintf(status_buffer + off, rem, "LO_TX:%s|LO_RX:%s|",
-                 tx_locked ? "LOCKED" : "UNLOCKED",
-                 rx_locked ? "LOCKED" : "UNLOCKED");
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+    snprintf(temp_buffer, sizeof(temp_buffer), "LO_TX:%s|LO_RX:%s|",
+             tx_locked ? "LOCKED" : "UNLOCKED",
+             rx_locked ? "LOCKED" : "UNLOCKED");
+    strcat(final_status, temp_buffer);

    // Temperature readings (8 variables)
+    // You'll need to populate these temperature values from your sensors
+    // For now, I'll show how to format them - replace with actual temperature readings
    Temperature_1 = ADS7830_Measure_SingleEnded(&hadc3, 0);
    Temperature_2 = ADS7830_Measure_SingleEnded(&hadc3, 1);
    Temperature_3 = ADS7830_Measure_SingleEnded(&hadc3, 2);
@@ -974,11 +961,11 @@ void getSystemStatusForGUI(char* status_buffer, size_t buffer_size) {
    Temperature_8 = ADS7830_Measure_SingleEnded(&hadc3, 7);

    // Format all 8 temperature variables
-    w = snprintf(status_buffer + off, rem,
-                 "T1:%.1f|T2:%.1f|T3:%.1f|T4:%.1f|T5:%.1f|T6:%.1f|T7:%.1f|T8:%.1f|",
-                 Temperature_1, Temperature_2, Temperature_3, Temperature_4,
-                 Temperature_5, Temperature_6, Temperature_7, Temperature_8);
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+    snprintf(temp_buffer, sizeof(temp_buffer),
+             "T1:%.1f|T2:%.1f|T3:%.1f|T4:%.1f|T5:%.1f|T6:%.1f|T7:%.1f|T8:%.1f|",
+             Temperature_1, Temperature_2, Temperature_3, Temperature_4,
+             Temperature_5, Temperature_6, Temperature_7, Temperature_8);
+    strcat(final_status, temp_buffer);

    // RF Power Amplifier status (if enabled)
    if (PowerAmplifier) {
@@ -988,17 +975,18 @@ void getSystemStatusForGUI(char* status_buffer, size_t buffer_size) {
        }
        avg_current /= 16.0f;

-        w = snprintf(status_buffer + off, rem, "PA_AvgCurrent:%.2f|PA_Enabled:%d|",
-                     avg_current, PowerAmplifier);
-        if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+        snprintf(temp_buffer, sizeof(temp_buffer), "PA_AvgCurrent:%.2f|PA_Enabled:%d|",
+                 avg_current, PowerAmplifier);
+        strcat(final_status, temp_buffer);
    }

    // Radar operation status
-    w = snprintf(status_buffer + off, rem, "BeamPos:%d|Azimuth:%d|ChirpCount:%d|",
-                 n, y, m);
-    if (w > 0 && (size_t)w < rem) { off += (size_t)w; rem -= (size_t)w; }
+    snprintf(temp_buffer, sizeof(temp_buffer), "BeamPos:%d|Azimuth:%d|ChirpCount:%d|",
+             n, y, m);
+    strcat(final_status, temp_buffer);

-    // NUL termination guaranteed by snprintf, but be safe
+    // Copy to output buffer
+    strncpy(status_buffer, final_status, buffer_size - 1);
    status_buffer[buffer_size - 1] = '\0';
 }

@@ -2007,13 +1995,12 @@ int main(void)
 	        HAL_UART_Transmit(&huart3, (uint8_t*)emergency_msg, strlen(emergency_msg), 1000);
 	        DIAG_ERR("SYS", "SAFE MODE ACTIVE -- blinking all LEDs, waiting for system_emergency_state clear");

-	        // Blink all LEDs to indicate safe mode (500ms period, visible to operator)
+	        // Blink all LEDs to indicate safe mode
 	        while (system_emergency_state) {
 	            HAL_GPIO_TogglePin(LED_1_GPIO_Port, LED_1_Pin);
 	            HAL_GPIO_TogglePin(LED_2_GPIO_Port, LED_2_Pin);
 	            HAL_GPIO_TogglePin(LED_3_GPIO_Port, LED_3_Pin);
 	            HAL_GPIO_TogglePin(LED_4_GPIO_Port, LED_4_Pin);
-	            HAL_Delay(250);
 	        }
 	        DIAG("SYS", "Exited safe mode blink loop -- system_emergency_state cleared");
 	    }
@@ -2127,16 +2114,6 @@ int main(void)

      runRadarPulseSequence();

-      /* [AGC] Outer-loop AGC: read FPGA saturation flag (DIG_5 / PD13),
-       * adjust ADAR1000 VGA common gain once per radar frame (~258 ms).
-       * Only run when AGC is enabled — otherwise leave VGA gains untouched. */
-      if (outerAgc.enabled) {
-          bool sat = HAL_GPIO_ReadPin(FPGA_DIG5_SAT_GPIO_Port,
-                                      FPGA_DIG5_SAT_Pin) == GPIO_PIN_SET;
-          outerAgc.update(sat);
-          outerAgc.applyGain(adarManager);
-      }
-
      /* [GAP-3 FIX 2] Kick hardware watchdog — if we don't reach here within
       * ~4 s, the IWDG resets the MCU automatically. */
      HAL_IWDG_Refresh(&hiwdg);
@@ -141,15 +141,6 @@ void Error_Handler(void);
 #define EN_DIS_RFPA_VDD_GPIO_Port GPIOD
 #define EN_DIS_COOLING_Pin GPIO_PIN_7
 #define EN_DIS_COOLING_GPIO_Port GPIOD
-
-/* FPGA digital I/O (directly connected GPIOs) */
-#define FPGA_DIG5_SAT_Pin       GPIO_PIN_13
-#define FPGA_DIG5_SAT_GPIO_Port GPIOD
-#define FPGA_DIG6_Pin           GPIO_PIN_14
-#define FPGA_DIG6_GPIO_Port     GPIOD
-#define FPGA_DIG7_Pin           GPIO_PIN_15
-#define FPGA_DIG7_GPIO_Port     GPIOD
-
 #define ADF4382_RX_CE_Pin GPIO_PIN_9
 #define ADF4382_RX_CE_GPIO_Port GPIOG
 #define ADF4382_RX_CS_Pin GPIO_PIN_10
@@ -18,9 +18,3 @@ test_bug12_pa_cal_loop_inverted
 test_bug13_dac2_adc_buffer_mismatch
 test_bug14_diag_section_args
 test_bug15_htim3_dangling_extern
-test_agc_outer_loop
-test_gap3_emergency_state_ordering
-test_gap3_emergency_stop_rails
-test_gap3_idq_periodic_reread
-test_gap3_iwdg_config
-test_gap3_temperature_max
@@ -16,17 +16,10 @@
 ################################################################################

 CC       := cc
-CXX      := c++
 CFLAGS   := -std=c11 -Wall -Wextra -Wno-unused-parameter -g -O0
-CXXFLAGS := -std=c++17 -Wall -Wextra -Wno-unused-parameter -g -O0
 # Shim headers come FIRST so they override real headers
 INCLUDES := -Ishims -I. -I../9_1_1_C_Cpp_Libraries

-# C++ library directory (AGC, ADAR1000 Manager)
-CXX_LIB_DIR := ../9_1_1_C_Cpp_Libraries
-CXX_SRCS    := $(CXX_LIB_DIR)/ADAR1000_AGC.cpp $(CXX_LIB_DIR)/ADAR1000_Manager.cpp
-CXX_OBJS    := ADAR1000_AGC.o ADAR1000_Manager.o
-
 # Real source files compiled against mock headers
 REAL_SRC := ../9_1_1_C_Cpp_Libraries/adf4382a_manager.c

@@ -69,10 +62,7 @@ TESTS_STANDALONE := test_bug12_pa_cal_loop_inverted \
 # Tests that need platform_noos_stm32.o + mocks
 TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only

-# C++ tests (AGC outer loop)
-TESTS_WITH_CXX := test_agc_outer_loop
-
-ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM) $(TESTS_WITH_CXX)
+ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM)

 .PHONY: all build test clean \
        $(addprefix test_,bug1 bug2 bug3 bug4 bug5 bug6 bug7 bug8 bug9 bug10 bug11 bug12 bug13 bug14 bug15) \
@@ -166,24 +156,6 @@ test_gap3_emergency_state_ordering: test_gap3_emergency_state_ordering.c
 $(TESTS_WITH_PLATFORM): %: %.c $(MOCK_OBJS) $(PLATFORM_OBJ)
 	$(CC) $(CFLAGS) $(INCLUDES) $< $(MOCK_OBJS) $(PLATFORM_OBJ) -o $@

-# --- C++ object rules ---
-
-ADAR1000_AGC.o: $(CXX_LIB_DIR)/ADAR1000_AGC.cpp $(CXX_LIB_DIR)/ADAR1000_AGC.h
-	$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $@
-
-ADAR1000_Manager.o: $(CXX_LIB_DIR)/ADAR1000_Manager.cpp $(CXX_LIB_DIR)/ADAR1000_Manager.h
-	$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $@
-
-# --- C++ test binary rules ---
-
-test_agc_outer_loop: test_agc_outer_loop.cpp $(CXX_OBJS) $(MOCK_OBJS)
-	$(CXX) $(CXXFLAGS) $(INCLUDES) $< $(CXX_OBJS) $(MOCK_OBJS) -o $@
-
-# Convenience target
-.PHONY: test_agc
-test_agc: test_agc_outer_loop
-	./test_agc_outer_loop
-
 # --- Individual test targets ---

 test_bug1: test_bug1_timed_sync_init_ordering
@@ -129,14 +129,6 @@ void Error_Handler(void);
 #define GYR_INT_Pin GPIO_PIN_8
 #define GYR_INT_GPIO_Port GPIOC

-/* FPGA digital I/O (directly connected GPIOs) */
-#define FPGA_DIG5_SAT_Pin       GPIO_PIN_13
-#define FPGA_DIG5_SAT_GPIO_Port GPIOD
-#define FPGA_DIG6_Pin           GPIO_PIN_14
-#define FPGA_DIG6_GPIO_Port     GPIOD
-#define FPGA_DIG7_Pin           GPIO_PIN_15
-#define FPGA_DIG7_GPIO_Port     GPIOD
-
 #ifdef __cplusplus
 }
 #endif
@@ -175,7 +175,7 @@ void HAL_Delay(uint32_t Delay)
    mock_tick += Delay;
 }

-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData,
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData,
                                     uint16_t Size, uint32_t Timeout)
 {
    spy_push((SpyRecord){
@@ -34,10 +34,6 @@ typedef uint32_t HAL_StatusTypeDef;

 #define HAL_MAX_DELAY 0xFFFFFFFFU

-#ifndef __NOP
-#define __NOP() ((void)0)
-#endif
-
 /* ========================= GPIO Types ============================ */

 typedef struct {
@@ -186,7 +182,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
 void          HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
 uint32_t      HAL_GetTick(void);
 void          HAL_Delay(uint32_t Delay);
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);

 /* ========================= SPI stubs ============================== */

@@ -1,361 +0,0 @@
-// test_agc_outer_loop.cpp -- C++ unit tests for ADAR1000_AGC outer-loop AGC
-//
-// Tests the STM32 outer-loop AGC class that adjusts ADAR1000 VGA gain based
-// on the FPGA's saturation flag.  Uses the existing HAL mock/spy framework.
-//
-// Build: c++ -std=c++17 ... (see Makefile TESTS_WITH_CXX rule)
-
-#include <cassert>
-#include <cstdio>
-#include <cstring>
-
-// Shim headers override real STM32/diag headers
-#include "stm32_hal_mock.h"
-#include "ADAR1000_AGC.h"
-#include "ADAR1000_Manager.h"
-
-// ---------------------------------------------------------------------------
-// Linker symbols required by ADAR1000_Manager.cpp (pulled in via main.h shim)
-// ---------------------------------------------------------------------------
-uint8_t GUI_start_flag_received = 0;
-uint8_t USB_Buffer[64] = {0};
-extern "C" void Error_Handler(void) {}
-
-// ---------------------------------------------------------------------------
-// Helpers
-// ---------------------------------------------------------------------------
-
-static int tests_passed = 0;
-static int tests_total  = 0;
-
-#define RUN_TEST(fn)                                                           \
-    do {                                                                        \
-        tests_total++;                                                          \
-        printf("  [%2d] %-55s ", tests_total, #fn);                            \
-        fn();                                                                   \
-        tests_passed++;                                                         \
-        printf("PASS\n");                                                       \
-    } while (0)
-
-// ---------------------------------------------------------------------------
-// Test 1: Default construction matches design spec
-// ---------------------------------------------------------------------------
-static void test_defaults()
-{
-    ADAR1000_AGC agc;
-
-    assert(agc.agc_base_gain == 30);  // kDefaultRxVgaGain
-    assert(agc.gain_step_down == 4);
-    assert(agc.gain_step_up == 1);
-    assert(agc.min_gain == 0);
-    assert(agc.max_gain == 127);
-    assert(agc.holdoff_frames == 4);
-    assert(agc.enabled == true);
-    assert(agc.holdoff_counter == 0);
-    assert(agc.last_saturated == false);
-    assert(agc.saturation_event_count == 0);
-
-    // All cal offsets zero
-    for (int i = 0; i < AGC_TOTAL_CHANNELS; ++i) {
-        assert(agc.cal_offset[i] == 0);
-    }
-}
-
-// ---------------------------------------------------------------------------
-// Test 2: Saturation reduces gain by step_down
-// ---------------------------------------------------------------------------
-static void test_saturation_reduces_gain()
-{
-    ADAR1000_AGC agc;
-    uint8_t initial = agc.agc_base_gain;  // 30
-
-    agc.update(true);  // saturation
-
-    assert(agc.agc_base_gain == initial - agc.gain_step_down);  // 26
-    assert(agc.last_saturated == true);
-    assert(agc.holdoff_counter == 0);
-}
-
-// ---------------------------------------------------------------------------
-// Test 3: Holdoff prevents premature gain-up
-// ---------------------------------------------------------------------------
-static void test_holdoff_prevents_early_gain_up()
-{
-    ADAR1000_AGC agc;
-    agc.update(true);  // saturate once -> gain = 26
-    uint8_t after_sat = agc.agc_base_gain;
-
-    // Feed (holdoff_frames - 1) clear frames — should NOT increase gain
-    for (uint8_t i = 0; i < agc.holdoff_frames - 1; ++i) {
-        agc.update(false);
-        assert(agc.agc_base_gain == after_sat);
-    }
-
-    // holdoff_counter should be holdoff_frames - 1
-    assert(agc.holdoff_counter == agc.holdoff_frames - 1);
-}
-
-// ---------------------------------------------------------------------------
-// Test 4: Recovery after holdoff period
-// ---------------------------------------------------------------------------
-static void test_recovery_after_holdoff()
-{
-    ADAR1000_AGC agc;
-    agc.update(true);  // saturate -> gain = 26
-    uint8_t after_sat = agc.agc_base_gain;
-
-    // Feed exactly holdoff_frames clear frames
-    for (uint8_t i = 0; i < agc.holdoff_frames; ++i) {
-        agc.update(false);
-    }
-
-    assert(agc.agc_base_gain == after_sat + agc.gain_step_up);  // 27
-    assert(agc.holdoff_counter == 0);  // reset after recovery
-}
-
-// ---------------------------------------------------------------------------
-// Test 5: Min gain clamping
-// ---------------------------------------------------------------------------
-static void test_min_gain_clamp()
-{
-    ADAR1000_AGC agc;
-    agc.min_gain = 10;
-    agc.agc_base_gain = 12;
-    agc.gain_step_down = 4;
-
-    agc.update(true);  // 12 - 4 = 8, but min = 10
-    assert(agc.agc_base_gain == 10);
-
-    agc.update(true);  // already at min
-    assert(agc.agc_base_gain == 10);
-}
-
-// ---------------------------------------------------------------------------
-// Test 6: Max gain clamping
-// ---------------------------------------------------------------------------
-static void test_max_gain_clamp()
-{
-    ADAR1000_AGC agc;
-    agc.max_gain = 32;
-    agc.agc_base_gain = 31;
-    agc.gain_step_up = 2;
-    agc.holdoff_frames = 1;  // immediate recovery
-
-    agc.update(false);  // 31 + 2 = 33, but max = 32
-    assert(agc.agc_base_gain == 32);
-
-    agc.update(false);  // already at max
-    assert(agc.agc_base_gain == 32);
-}
-
-// ---------------------------------------------------------------------------
-// Test 7: Per-channel calibration offsets
-// ---------------------------------------------------------------------------
-static void test_calibration_offsets()
-{
-    ADAR1000_AGC agc;
-    agc.agc_base_gain = 30;
-    agc.min_gain = 0;
-    agc.max_gain = 60;
-
-    agc.cal_offset[0]  =  5;   // 30 + 5  = 35
-    agc.cal_offset[1]  = -10;  // 30 - 10 = 20
-    agc.cal_offset[15] =  40;  // 30 + 40 = 60 (clamped to max)
-
-    assert(agc.effectiveGain(0) == 35);
-    assert(agc.effectiveGain(1) == 20);
-    assert(agc.effectiveGain(15) == 60);  // clamped to max_gain
-
-    // Negative clamp
-    agc.cal_offset[2] = -50;   // 30 - 50 = -20, clamped to min_gain = 0
-    assert(agc.effectiveGain(2) == 0);
-
-    // Out-of-range index returns min_gain
-    assert(agc.effectiveGain(16) == agc.min_gain);
-}
-
-// ---------------------------------------------------------------------------
-// Test 8: Disabled AGC is a no-op
-// ---------------------------------------------------------------------------
-static void test_disabled_noop()
-{
-    ADAR1000_AGC agc;
-    agc.enabled = false;
-    uint8_t original = agc.agc_base_gain;
-
-    agc.update(true);   // should be ignored
-    assert(agc.agc_base_gain == original);
-    assert(agc.last_saturated == false);  // not updated when disabled
-    assert(agc.saturation_event_count == 0);
-
-    agc.update(false);  // also ignored
-    assert(agc.agc_base_gain == original);
-}
-
-// ---------------------------------------------------------------------------
-// Test 9: applyGain() produces correct SPI writes
-// ---------------------------------------------------------------------------
-static void test_apply_gain_spi()
-{
-    spy_reset();
-
-    ADAR1000Manager mgr;  // creates 4 devices
-    ADAR1000_AGC agc;
-    agc.agc_base_gain = 42;
-
-    agc.applyGain(mgr);
-
-    // Each channel: adarSetRxVgaGain -> adarWrite(gain) + adarWrite(LOAD_WORKING)
-    // Each adarWrite: CS_low (GPIO_WRITE) + SPI_TRANSMIT + CS_high (GPIO_WRITE)
-    // = 3 spy records per adarWrite
-    // = 6 spy records per channel
-    // = 16 channels * 6 = 96 total spy records
-
-    // Verify SPI transmit count: 2 SPI calls per channel * 16 channels = 32
-    int spi_count = spy_count_type(SPY_SPI_TRANSMIT);
-    assert(spi_count == 32);
-
-    // Verify GPIO write count: 4 GPIO writes per channel (CS low + CS high for each of 2 adarWrite calls)
-    int gpio_writes = spy_count_type(SPY_GPIO_WRITE);
-    assert(gpio_writes == 64);  // 16 ch * 2 adarWrite * 2 GPIO each
-}
-
-// ---------------------------------------------------------------------------
-// Test 10: resetState() clears counters but preserves config
-// ---------------------------------------------------------------------------
-static void test_reset_preserves_config()
-{
-    ADAR1000_AGC agc;
-    agc.agc_base_gain = 42;
-    agc.gain_step_down = 8;
-    agc.cal_offset[3] = -5;
-
-    // Generate some state
-    agc.update(true);
-    agc.update(true);
-    assert(agc.saturation_event_count == 2);
-    assert(agc.last_saturated == true);
-
-    agc.resetState();
-
-    // State cleared
-    assert(agc.holdoff_counter == 0);
-    assert(agc.last_saturated == false);
-    assert(agc.saturation_event_count == 0);
-
-    // Config preserved
-    assert(agc.agc_base_gain == 42 - 8 - 8);  // two saturations applied before reset
-    assert(agc.gain_step_down == 8);
-    assert(agc.cal_offset[3] == -5);
-}
-
-// ---------------------------------------------------------------------------
-// Test 11: Saturation counter increments correctly
-// ---------------------------------------------------------------------------
-static void test_saturation_counter()
-{
-    ADAR1000_AGC agc;
-
-    for (int i = 0; i < 10; ++i) {
-        agc.update(true);
-    }
-    assert(agc.saturation_event_count == 10);
-
-    // Clear frames don't increment saturation count
-    for (int i = 0; i < 5; ++i) {
-        agc.update(false);
-    }
-    assert(agc.saturation_event_count == 10);
-}
-
-// ---------------------------------------------------------------------------
-// Test 12: Mixed saturation/clear sequence
-// ---------------------------------------------------------------------------
-static void test_mixed_sequence()
-{
-    ADAR1000_AGC agc;
-    agc.agc_base_gain = 30;
-    agc.gain_step_down = 4;
-    agc.gain_step_up = 1;
-    agc.holdoff_frames = 3;
-
-    // Saturate: 30 -> 26
-    agc.update(true);
-    assert(agc.agc_base_gain == 26);
-    assert(agc.holdoff_counter == 0);
-
-    // 2 clear frames (not enough for recovery)
-    agc.update(false);
-    agc.update(false);
-    assert(agc.agc_base_gain == 26);
-    assert(agc.holdoff_counter == 2);
-
-    // Saturate again: 26 -> 22, counter resets
-    agc.update(true);
-    assert(agc.agc_base_gain == 22);
-    assert(agc.holdoff_counter == 0);
-    assert(agc.saturation_event_count == 2);
-
-    // 3 clear frames -> recovery: 22 -> 23
-    agc.update(false);
-    agc.update(false);
-    agc.update(false);
-    assert(agc.agc_base_gain == 23);
-    assert(agc.holdoff_counter == 0);
-
-    // 3 more clear -> 23 -> 24
-    agc.update(false);
-    agc.update(false);
-    agc.update(false);
-    assert(agc.agc_base_gain == 24);
-}
-
-// ---------------------------------------------------------------------------
-// Test 13: Effective gain with edge-case base_gain values
-// ---------------------------------------------------------------------------
-static void test_effective_gain_edge_cases()
-{
-    ADAR1000_AGC agc;
-    agc.min_gain = 5;
-    agc.max_gain = 250;
-
-    // Base gain at zero with positive offset
-    agc.agc_base_gain = 0;
-    agc.cal_offset[0] = 3;
-    assert(agc.effectiveGain(0) == 5);  // 0 + 3 = 3, clamped to min_gain=5
-
-    // Base gain at max with zero offset
-    agc.agc_base_gain = 250;
-    agc.cal_offset[0] = 0;
-    assert(agc.effectiveGain(0) == 250);
-
-    // Base gain at max with positive offset -> clamped
-    agc.agc_base_gain = 250;
-    agc.cal_offset[0] = 10;
-    assert(agc.effectiveGain(0) == 250);  // clamped to max_gain
-}
-
-// ---------------------------------------------------------------------------
-// main
-// ---------------------------------------------------------------------------
-int main()
-{
-    printf("=== ADAR1000_AGC Outer-Loop Unit Tests ===\n");
-
-    RUN_TEST(test_defaults);
-    RUN_TEST(test_saturation_reduces_gain);
-    RUN_TEST(test_holdoff_prevents_early_gain_up);
-    RUN_TEST(test_recovery_after_holdoff);
-    RUN_TEST(test_min_gain_clamp);
-    RUN_TEST(test_max_gain_clamp);
-    RUN_TEST(test_calibration_offsets);
-    RUN_TEST(test_disabled_noop);
-    RUN_TEST(test_apply_gain_spi);
-    RUN_TEST(test_reset_preserves_config);
-    RUN_TEST(test_saturation_counter);
-    RUN_TEST(test_mixed_sequence);
-    RUN_TEST(test_effective_gain_edge_cases);
-
-    printf("=== Results: %d/%d passed ===\n", tests_passed, tests_total);
-    return (tests_passed == tests_total) ? 0 : 1;
-}
@@ -212,11 +212,6 @@ BUFG bufg_feedback (

 // ---- Output BUFG ----
 // Routes the jitter-cleaned 400 MHz CLKOUT0 onto a global clock network.
-// DONT_TOUCH prevents phys_opt_design AggressiveExplore from replicating this
-// BUFG into a cascaded chain (4 BUFGs in series observed in Build 26), which
-// added ~243ps of clock insertion delay and caused -187ps clock skew on the
-// NCO→DSP mixer critical path.
-(* DONT_TOUCH = "TRUE" *)
 BUFG bufg_clk400m (
    .I(clk_mmcm_out0),
    .O(clk_400m_out)
@@ -66,13 +66,13 @@ reg signed [COMB_WIDTH-1:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
 // Pipeline valid for comb stages 1-4: delayed by 1 cycle vs comb_pipe to
 // account for CREG+AREG+BREG pipeline inside comb_0_dsp (explicit DSP48E1).
 // Comb[0] result appears 1 cycle after data_valid_comb_pipe.
-(* keep = "true", max_fanout = 16 *) reg data_valid_comb_0_out;
+(* keep = "true", max_fanout = 4 *) reg data_valid_comb_0_out;

 // Enhanced control and monitoring
 reg [1:0] decimation_counter;
-(* keep = "true", max_fanout = 16 *) reg data_valid_delayed;
-(* keep = "true", max_fanout = 16 *) reg data_valid_comb;
-(* keep = "true", max_fanout = 16 *) reg data_valid_comb_pipe;
+(* keep = "true", max_fanout = 4 *) reg data_valid_delayed;
+(* keep = "true", max_fanout = 4 *) reg data_valid_comb;
+(* keep = "true", max_fanout = 4 *) reg data_valid_comb_pipe;
 reg [7:0] output_counter;
 reg [ACC_WIDTH-1:0] max_integrator_value;
 reg overflow_detected;
@@ -83,13 +83,3 @@ set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
 # Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
 # for source-synchronous LVDS ADC interfaces using BUFIO capture.
 set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
-
-# --------------------------------------------------------------------------
-# Timing margin for 400 MHz critical paths
-# --------------------------------------------------------------------------
-# Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
-# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
-# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
-# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
-# This is additive to the existing jitter-based uncertainty (~53 ps).
-set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]
@@ -222,16 +222,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
 set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 # reset_n is DIG_4 (PD12) — constrained above in the RESET section

-# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — FPGA→STM32 status outputs
-# DIG_5: AGC saturation flag (PD13 on STM32)
-# DIG_6: reserved (PD14)
-# DIG_7: reserved (PD15)
-set_property PACKAGE_PIN H11 [get_ports {gpio_dig5}]
-set_property PACKAGE_PIN G12 [get_ports {gpio_dig6}]
-set_property PACKAGE_PIN H12 [get_ports {gpio_dig7}]
-set_property IOSTANDARD LVCMOS33 [get_ports {gpio_dig*}]
-set_property DRIVE 8 [get_ports {gpio_dig*}]
-set_property SLEW SLOW [get_ports {gpio_dig*}]
+# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — available for FPGA→STM32 status
+# Currently unused in RTL. Could be connected to status outputs if needed.

 # ============================================================================
 # ADC INTERFACE (LVDS — Bank 14, VCCO=3.3V)
@@ -102,19 +102,14 @@ wire signed [17:0] debug_mixed_q_trunc;
 reg [7:0] signal_power_i, signal_power_q;

 // Internal mixing signals
-// Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
-// The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
-// (1.505ns routing in Build 26, WNS=+0.002ns). With BREG=1 still active inside the DSP,
-// total latency increases by 1 cycle (2.5ns at 400MHz — negligible for radar).
+// DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 handles all internal pipelining
+// Latency: 4 cycles (1 for AREG/BREG, 1 for MREG, 1 for PREG, 1 for post-DSP retiming)
 wire signed [MIXER_WIDTH-1:0] adc_signed_w;
 reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
 reg mixed_valid;
 reg mixer_overflow_i, mixer_overflow_q;
-// Pipeline valid tracking: 5-stage shift register (1 NCO pipe + 3 DSP48E1 + 1 retiming)
-reg [4:0] dsp_valid_pipe;
-// NCO→DSP pipeline registers — breaks the long NCO sin/cos → DSP48E1 B-port route
-// DONT_TOUCH prevents Vivado from absorbing these into the DSP or optimizing away
-(* DONT_TOUCH = "TRUE" *) reg signed [15:0] cos_nco_pipe, sin_nco_pipe;
+// Pipeline valid tracking: 4-stage shift register (3 for DSP48E1 + 1 for post-DSP retiming)
+reg [3:0] dsp_valid_pipe;
 // Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
 // This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
 // ensuring WNS > 0 at 400 MHz regardless of placement seed
@@ -215,11 +210,11 @@ nco_400m_enhanced nco_core (
 //
 // Architecture:
 //   ADC data → sign-extend to 18b → DSP48E1 A-port (AREG=1 pipelines it)
-//   NCO cos/sin → fabric pipeline reg → DSP48E1 B-port (BREG=1 pipelines it)
+//   NCO cos/sin → sign-extend to 18b → DSP48E1 B-port (BREG=1 pipelines it)
 //   Multiply result captured by MREG=1, then output registered by PREG=1
 //   force_saturation override applied AFTER DSP48E1 output (not on input path)
 //
-// Latency: 4 clock cycles (1 NCO pipe + 1 AREG/BREG + 1 MREG + 1 PREG) + 1 retiming = 5 total
+// Latency: 3 clock cycles (AREG/BREG + MREG + PREG)
 // PREG=1 absorbs DSP48E1 CLK→P delay internally, preventing fabric timing violations
 // In simulation (Icarus), uses behavioral equivalent since DSP48E1 is Xilinx-only
 // ============================================================================
@@ -228,35 +223,24 @@ nco_400m_enhanced nco_core (
 assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} - 
                      {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;

-// Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
+// Valid pipeline: 4-stage shift register (3 for DSP48E1 AREG+MREG+PREG + 1 for retiming)
 always @(posedge clk_400m or negedge reset_n_400m) begin
    if (!reset_n_400m) begin
-        dsp_valid_pipe <= 5'b00000;
+        dsp_valid_pipe <= 4'b0000;
    end else begin
-        dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
+        dsp_valid_pipe <= {dsp_valid_pipe[2:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
    end
 end

 `ifdef SIMULATION
 // ---- Behavioral model for Icarus Verilog simulation ----
-// Mimics NCO pipeline + DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 (4-cycle DSP + 1 NCO pipe)
+// Mimics DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 (3-cycle latency)
 reg signed [MIXER_WIDTH-1:0] adc_signed_reg;     // Models AREG
 reg signed [15:0] cos_pipe_reg, sin_pipe_reg;     // Models BREG
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Models MREG
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG

-// Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
-        cos_nco_pipe <= 0;
-        sin_nco_pipe <= 0;
-    end else begin
-        cos_nco_pipe <= cos_out;
-        sin_nco_pipe <= sin_out;
-    end
-end
-
-// Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
+// Stage 1: AREG/BREG equivalent
 always @(posedge clk_400m or negedge reset_n_400m) begin
    if (!reset_n_400m) begin
        adc_signed_reg <= 0;
@@ -264,8 +248,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
        sin_pipe_reg <= 0;
    end else begin
        adc_signed_reg <= adc_signed_w;
-        cos_pipe_reg <= cos_nco_pipe;
-        sin_pipe_reg <= sin_nco_pipe;
+        cos_pipe_reg <= cos_out;
+        sin_pipe_reg <= sin_out;
    end
 end

@@ -307,20 +291,6 @@ end
 // This guarantees AREG/BREG/MREG are used, achieving timing closure at 400 MHz
 wire [47:0] dsp_p_i, dsp_p_q;

-// NCO pipeline stage — breaks the long NCO sin/cos → DSP48E1 B-port route
-// (1.505ns routing observed in Build 26). These fabric registers are placed
-// near the DSP by the placer, splitting the route into two shorter segments.
-// DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m or negedge reset_n_400m) begin
-    if (!reset_n_400m) begin
-        cos_nco_pipe <= 0;
-        sin_nco_pipe <= 0;
-    end else begin
-        cos_nco_pipe <= cos_out;
-        sin_nco_pipe <= sin_out;
-    end
-end
-
 // DSP48E1 for I-channel mixer (adc_signed * cos_out)
 DSP48E1 #(
    // Feature control attributes
@@ -380,7 +350,7 @@ DSP48E1 #(
    .CEINMODE(1'b0),
    // Data ports
    .A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}),   // Sign-extend 18b to 30b
-    .B({{2{cos_nco_pipe[15]}}, cos_nco_pipe}),                // Sign-extend 16b to 18b (pipelined)
+    .B({{2{cos_out[15]}}, cos_out}),                          // Sign-extend 16b to 18b
    .C(48'b0),
    .D(25'b0),
    .CARRYIN(1'b0),
@@ -462,7 +432,7 @@ DSP48E1 #(
    .CED(1'b0),
    .CEINMODE(1'b0),
    .A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}),
-    .B({{2{sin_nco_pipe[15]}}, sin_nco_pipe}),
+    .B({{2{sin_out[15]}}, sin_out}),
    .C(48'b0),
    .D(25'b0),
    .CARRYIN(1'b0),
@@ -522,7 +492,7 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
        mixer_overflow_q <= 0;
        saturation_count <= 0;
        overflow_detected <= 0;
-    end else if (dsp_valid_pipe[4]) begin
+    end else if (dsp_valid_pipe[3]) begin
        // Force saturation for testing (applied after DSP output, not on input path)
        if (force_saturation_sync) begin
            mixed_i <= 34'h1FFFFFFFF;
@@ -296,7 +296,7 @@ always @(posedge clk or negedge reset_n) begin
                    state           <= ST_DONE;
                end
            end
-            // Timeout: if no ADC data after 1000 cycles (10 us @ 100 MHz), FAIL
+            // Timeout: if no ADC data after 10000 cycles, FAIL
            step_cnt <= step_cnt + 1;
            if (step_cnt >= 10'd1000 && adc_cap_cnt == 0) begin
                result_flags[4] <= 1'b0;
@@ -18,9 +18,10 @@ module matched_filter_multi_segment (
    input wire mc_new_elevation,    // Toggle for new elevation (32)
    input wire mc_new_azimuth,      // Toggle for new azimuth (50)
    
-    // Reference chirp (upstream memory loader selects long/short via use_long_chirp)
-    input wire [15:0] ref_chirp_real,
-    input wire [15:0] ref_chirp_imag,
+    input wire [15:0] long_chirp_real,
+    input wire [15:0] long_chirp_imag,
+    input wire [15:0] short_chirp_real,
+    input wire [15:0] short_chirp_imag,
    
    // Memory system interface
    output reg [1:0] segment_request,
@@ -243,7 +244,6 @@ always @(posedge clk or negedge reset_n) begin
                    if (!use_long_chirp) begin
                        if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                            state <= ST_ZERO_PAD;
-                            chirp_complete <= 1;  // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
                            `ifdef SIMULATION
                            $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                     chirp_samples_collected + 1);
@@ -500,9 +500,11 @@ matched_filter_processing_chain m_f_p_c(
    // Chirp Selection
    .chirp_counter(chirp_counter),
    
-    // Reference Chirp Memory Interface (single pair — upstream selects long/short)
-    .ref_chirp_real(ref_chirp_real),
-    .ref_chirp_imag(ref_chirp_imag),
+    // Reference Chirp Memory Interfaces
+    .long_chirp_real(long_chirp_real),
+    .long_chirp_imag(long_chirp_imag),
+    .short_chirp_real(short_chirp_real),
+    .short_chirp_imag(short_chirp_imag),
    
    // Output
    .range_profile_i(fft_pc_i),
@@ -15,7 +15,7 @@
 *   .clk, .reset_n
 *   .adc_data_i, .adc_data_q, .adc_valid      <- from input buffer
 *   .chirp_counter                              <- 6-bit frame counter
- *   .ref_chirp_real/imag                     <- reference (time-domain)
+ *   .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
 *   .range_profile_i, .range_profile_q, .range_profile_valid -> output
 *   .chain_state                                -> 4-bit status
 *
@@ -48,10 +48,10 @@ module matched_filter_processing_chain (
    input wire [5:0] chirp_counter,

    // Reference chirp (time-domain, latency-aligned by upstream buffer)
-    // Upstream chirp_memory_loader_param selects long/short reference
-    // via use_long_chirp — this single pair carries whichever is active.
-    input wire [15:0] ref_chirp_real,
-    input wire [15:0] ref_chirp_imag,
+    input wire [15:0] long_chirp_real,
+    input wire [15:0] long_chirp_imag,
+    input wire [15:0] short_chirp_real,
+    input wire [15:0] short_chirp_imag,

    // Output: range profile (pulse-compressed)
    output wire signed [15:0] range_profile_i,
@@ -189,8 +189,8 @@ always @(posedge clk or negedge reset_n) begin
                // Store first sample (signal + reference)
                fwd_buf_i[0] <= $signed(adc_data_i);
                fwd_buf_q[0] <= $signed(adc_data_q);
-                ref_buf_i[0] <= $signed(ref_chirp_real);
-                ref_buf_q[0] <= $signed(ref_chirp_imag);
+                ref_buf_i[0] <= $signed(long_chirp_real);
+                ref_buf_q[0] <= $signed(long_chirp_imag);
                fwd_in_count <= 1;
                state        <= ST_FWD_FFT;
            end
@@ -205,8 +205,8 @@ always @(posedge clk or negedge reset_n) begin
                if (adc_valid && fwd_in_count < FFT_SIZE) begin
                    fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
                    fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
-                    ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
-                    ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
+                    ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
+                    ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
                    fwd_in_count <= fwd_in_count + 1;
                end

@@ -775,16 +775,16 @@ always @(posedge clk) begin : ref_bram_port
        if (adc_valid) begin
            we      = 1'b1;
            addr    = 0;
-            wdata_i = $signed(ref_chirp_real);
-            wdata_q = $signed(ref_chirp_imag);
+            wdata_i = $signed(long_chirp_real);
+            wdata_q = $signed(long_chirp_imag);
        end
    end
    ST_COLLECT: begin
        if (adc_valid && collect_count < FFT_SIZE) begin
            we      = 1'b1;
            addr    = collect_count[ADDR_BITS-1:0];
-            wdata_i = $signed(ref_chirp_real);
-            wdata_q = $signed(ref_chirp_imag);
+            wdata_i = $signed(long_chirp_real);
+            wdata_q = $signed(long_chirp_imag);
        end
    end
    ST_REF_FFT: begin
@@ -1,200 +0,0 @@
-// ============================================================================
-// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
-// ============================================================================
-//
-// ALL modules in the FPGA processing chain MUST `include this file instead of
-// hardcoding range bins, segment counts, chirp samples, or timing values.
-//
-// This file uses `define macros (not localparam) so it can be included at any
-// scope. Each consuming module should include this file inside its body and
-// optionally alias macros to localparams for readability.
-//
-// BOARD VARIANTS:
-//   SUPPORT_LONG_RANGE = 0  (50T, USB_MODE=1)  — 3 km mode only, 64 range bins
-//   SUPPORT_LONG_RANGE = 1  (200T, USB_MODE=0) — 3 km + 20 km modes, up to 1024 bins
-//
-// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
-//   2'b00 = 3 km  (default on both boards)
-//   2'b01 = 20 km (200T only; clamped to 3 km on 50T)
-//   2'b10 = Reserved
-//   2'b11 = Reserved
-//
-// USAGE:
-//   `include "radar_params.vh"
-//   Then reference `RP_FFT_SIZE, `RP_MAX_OUTPUT_BINS, etc.
-//
-// PHYSICAL CONSTANTS (derived from hardware):
-//   ADC clock:           400 MSPS
-//   CIC decimation:      4x
-//   Processing rate:     100 MSPS (post-DDC)
-//   Range per sample:    c / (2 * 100e6) = 1.5 m
-//   Decimation factor:   16 (1024 FFT bins -> 64 output bins per segment)
-//   Range per dec. bin:  1.5 m * 16 = 24.0 m
-//   Carrier frequency:   10.5 GHz
-//
-// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
-//   Range resolution:    c / (2 * BW)
-//     20 MHz -> 7.5 m
-//     30 MHz -> 5.0 m
-//   NOTE: Range resolution is independent of range-per-bin. Resolution
-//   determines the minimum separation between two targets; range-per-bin
-//   determines the spatial sampling grid.
-// ============================================================================
-
-`ifndef RADAR_PARAMS_VH
-`define RADAR_PARAMS_VH
-
-// ============================================================================
-// BOARD VARIANT — set at synthesis time, NOT runtime
-// ============================================================================
-// Default to 50T (conservative). Override in top-level or synthesis script:
-//   +define+SUPPORT_LONG_RANGE
-// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
-
-// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
-// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
-// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
-
-// ============================================================================
-// FFT AND PROCESSING CONSTANTS (fixed, both modes)
-// ============================================================================
-
-`define RP_FFT_SIZE             1024    // Range FFT points per segment
-`define RP_OVERLAP_SAMPLES      128     // Overlap between adjacent segments
-`define RP_SEGMENT_ADVANCE      896     // FFT_SIZE - OVERLAP = 1024 - 128
-`define RP_DECIMATION_FACTOR    16      // Range bin decimation (1024 -> 64)
-`define RP_BINS_PER_SEGMENT     64      // FFT_SIZE / DECIMATION_FACTOR
-`define RP_DOPPLER_FFT_SIZE     16      // Per sub-frame Doppler FFT
-`define RP_CHIRPS_PER_FRAME     32      // Total chirps (16 long + 16 short)
-`define RP_CHIRPS_PER_SUBFRAME  16      // Chirps per Doppler sub-frame
-`define RP_NUM_DOPPLER_BINS     32      // 2 sub-frames * 16 = 32
-`define RP_DATA_WIDTH           16      // ADC/processing data width
-
-// ============================================================================
-// 3 KM MODE PARAMETERS (both 50T and 200T)
-// ============================================================================
-
-`define RP_LONG_CHIRP_SAMPLES_3KM   3000    // 30 us at 100 MSPS
-`define RP_LONG_SEGMENTS_3KM        4       // ceil((3000-1024)/896) + 1 = 4
-`define RP_OUTPUT_RANGE_BINS_3KM    64      // Downstream pipeline expects 64 range bins (NOTE: will become 128 after 2048-pt FFT upgrade)
-`define RP_SHORT_CHIRP_SAMPLES      50      // 0.5 us at 100 MSPS (same both modes)
-`define RP_SHORT_SEGMENTS           1       // Single segment for short chirp
-
-// Derived 3 km limits
-`define RP_MAX_RANGE_3KM            1536    // 64 bins * 24 m = 1536 m
-
-// ============================================================================
-// 20 KM MODE PARAMETERS (200T only)
-// ============================================================================
-
-`define RP_LONG_CHIRP_SAMPLES_20KM  13700   // 137 us at 100 MSPS (= listen window)
-`define RP_LONG_SEGMENTS_20KM       16      // ceil((13700-1024)/896) + 1 = 16
-`define RP_OUTPUT_RANGE_BINS_20KM   1024    // 16 segments * 64 dec. bins each
-
-// Derived 20 km limits
-`define RP_MAX_RANGE_20KM           24576   // 1024 bins * 24 m = 24576 m
-
-// ============================================================================
-// MAX VALUES (for sizing buffers — compile-time, based on board variant)
-// ============================================================================
-
-`ifdef SUPPORT_LONG_RANGE
-  `define RP_MAX_SEGMENTS           16
-  `define RP_MAX_OUTPUT_BINS        1024
-  `define RP_MAX_CHIRP_SAMPLES      13700
-`else
-  `define RP_MAX_SEGMENTS           4
-  `define RP_MAX_OUTPUT_BINS        64
-  `define RP_MAX_CHIRP_SAMPLES      3000
-`endif
-
-// ============================================================================
-// BIT WIDTHS (derived from MAX values)
-// ============================================================================
-
-// Segment index: ceil(log2(MAX_SEGMENTS))
-//   50T:  log2(4)  = 2 bits
-//   200T: log2(16) = 4 bits
-`ifdef SUPPORT_LONG_RANGE
-  `define RP_SEGMENT_IDX_WIDTH      4
-  `define RP_RANGE_BIN_WIDTH        10
-  `define RP_CHIRP_MEM_ADDR_W       14      // log2(16*1024) = 14
-  `define RP_DOPPLER_MEM_ADDR_W     15      // log2(1024*32) = 15
-  `define RP_CFAR_MAG_ADDR_W        15      // log2(1024*32) = 15
-`else
-  `define RP_SEGMENT_IDX_WIDTH      2
-  `define RP_RANGE_BIN_WIDTH        6
-  `define RP_CHIRP_MEM_ADDR_W       12      // log2(4*1024) = 12
-  `define RP_DOPPLER_MEM_ADDR_W     11      // log2(64*32) = 11
-  `define RP_CFAR_MAG_ADDR_W        11      // log2(64*32) = 11
-`endif
-
-// Derived depths (for memory declarations)
-// Usage: reg [15:0] mem [0:`RP_CHIRP_MEM_DEPTH-1];
-`define RP_CHIRP_MEM_DEPTH      (`RP_MAX_SEGMENTS * `RP_FFT_SIZE)
-`define RP_DOPPLER_MEM_DEPTH    (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
-`define RP_CFAR_MAG_DEPTH       (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
-
-// ============================================================================
-// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
-// ============================================================================
-// Reset defaults for host-configurable timing registers.
-// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
-
-`define RP_DEF_LONG_CHIRP_CYCLES    3000    // 30 us
-`define RP_DEF_LONG_LISTEN_CYCLES   13700   // 137 us
-`define RP_DEF_GUARD_CYCLES         17540   // 175.4 us
-`define RP_DEF_SHORT_CHIRP_CYCLES   50      // 0.5 us
-`define RP_DEF_SHORT_LISTEN_CYCLES  17450   // 174.5 us
-`define RP_DEF_CHIRPS_PER_ELEV      32
-
-// ============================================================================
-// BLIND ZONE CONSTANTS (informational, for comments and GUI)
-// ============================================================================
-// Long chirp blind zone:  c * 30 us / 2 = 4500 m
-// Short chirp blind zone: c * 0.5 us / 2 = 75 m
-
-`define RP_LONG_BLIND_ZONE_M        4500
-`define RP_SHORT_BLIND_ZONE_M       75
-
-// ============================================================================
-// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
-// ============================================================================
-// Range per ADC sample:     1.5 m  (stored as 15 in units of 0.1 m)
-// Range per decimated bin: 24.0 m  (stored as 240 in units of 0.1 m)
-// Processing rate:         100 MSPS
-
-`define RP_RANGE_PER_SAMPLE_DM      15      // 1.5 m in decimeters
-`define RP_RANGE_PER_BIN_DM         240     // 24.0 m in decimeters
-`define RP_PROCESSING_RATE_MHZ      100
-
-// ============================================================================
-// AGC DEFAULTS
-// ============================================================================
-`define RP_DEF_AGC_TARGET           200
-`define RP_DEF_AGC_ATTACK           1
-`define RP_DEF_AGC_DECAY            1
-`define RP_DEF_AGC_HOLDOFF          4
-
-// ============================================================================
-// CFAR DEFAULTS
-// ============================================================================
-`define RP_DEF_CFAR_GUARD           2
-`define RP_DEF_CFAR_TRAIN           8
-`define RP_DEF_CFAR_ALPHA           8'h30   // 3.0 in Q4.4
-`define RP_DEF_CFAR_MODE            2'b00   // CA-CFAR
-
-// ============================================================================
-// DETECTION DEFAULTS
-// ============================================================================
-`define RP_DEF_DETECT_THRESHOLD     10000
-
-// ============================================================================
-// RANGE MODE ENCODING
-// ============================================================================
-`define RP_RANGE_MODE_3KM           2'b00
-`define RP_RANGE_MODE_20KM          2'b01
-`define RP_RANGE_MODE_RSVD2         2'b10
-`define RP_RANGE_MODE_RSVD3         2'b11
-
-`endif // RADAR_PARAMS_VH
@@ -42,13 +42,6 @@ module radar_receiver_final (
    // [2:0]=shift amount: 0..7 bits. Default 0 = pass-through.
    input wire [3:0] host_gain_shift,

-    // AGC configuration (opcodes 0x28-0x2C, active only when agc_enable=1)
-    input wire        host_agc_enable,      // 0x28: 0=manual, 1=auto AGC
-    input wire [7:0]  host_agc_target,      // 0x29: target peak magnitude
-    input wire [3:0]  host_agc_attack,      // 0x2A: gain-down step on clipping
-    input wire [3:0]  host_agc_decay,       // 0x2B: gain-up step when weak
-    input wire [3:0]  host_agc_holdoff,     // 0x2C: frames before gain-up
-
    // STM32 toggle signals for mode 00 (STM32-driven) pass-through.
    // These are CDC-synchronized in radar_system_top.v / radar_transmitter.v
    // before reaching this module. In mode 00, the RX mode controller uses
@@ -67,12 +60,7 @@ module radar_receiver_final (
    // ADC raw data tap (clk_100m domain, post-DDC, for self-test / debug)
    output wire [15:0] dbg_adc_i,            // DDC output I (16-bit signed, 100 MHz)
    output wire [15:0] dbg_adc_q,            // DDC output Q (16-bit signed, 100 MHz)
-    output wire        dbg_adc_valid,        // DDC output valid (100 MHz)
-
-    // AGC status outputs (for status readback / STM32 outer loop)
-    output wire [7:0]  agc_saturation_count, // Per-frame clipped sample count
-    output wire [7:0]  agc_peak_magnitude,   // Per-frame peak (upper 8 bits)
-    output wire [3:0]  agc_current_gain      // Effective gain_shift encoding
+    output wire        dbg_adc_valid         // DDC output valid (100 MHz)
 );

 // ========== INTERNAL SIGNALS ==========
@@ -98,13 +86,11 @@ wire adc_valid_sync;
 // Gain-controlled signals (between DDC output and matched filter)
 wire signed [15:0] gc_i, gc_q;
 wire gc_valid;
-wire [7:0] gc_saturation_count;  // Diagnostic: per-frame clipped sample counter
-wire [7:0] gc_peak_magnitude;    // Diagnostic: per-frame peak magnitude
-wire [3:0] gc_current_gain;      // Diagnostic: effective gain_shift
+wire [7:0] gc_saturation_count;  // Diagnostic: clipped sample counter

-// Reference signal for the processing chain (carries long OR short ref
-// depending on use_long_chirp — selected by chirp_memory_loader_param)
-wire [15:0] ref_chirp_real, ref_chirp_imag;
+// Reference signals for the processing chain
+wire [15:0] long_chirp_real, long_chirp_imag;
+wire [15:0] short_chirp_real, short_chirp_imag;

 // ========== DOPPLER PROCESSING SIGNALS ==========
 wire [31:0] range_data_32bit;
@@ -174,7 +160,7 @@ wire clk_400m;
 // the buffered 400MHz DCO clock via adc_dco_bufg, avoiding duplicate
 // IBUFDS instantiations on the same LVDS clock pair.

-// 1. ADC + CDC + Digital Gain
+// 1. ADC + CDC + AGC

 // CMOS Output Interface (400MHz Domain)
 wire [7:0] adc_data_cmos;  // 8-bit ADC data (CMOS, from ad9484_interface_400m)
@@ -236,10 +222,9 @@ ddc_input_interface ddc_if (
    .data_sync_error()
 );

-// 2b. Digital Gain Control with AGC
+// 2b. Digital Gain Control (Fix 3)
 // Host-configurable power-of-2 shift between DDC output and matched filter.
-// Default gain_shift=0, agc_enable=0 → pass-through (no behavioral change).
-// When agc_enable=1: auto-adjusts gain per frame based on peak/saturation.
+// Default gain_shift=0 → pass-through (no behavioral change from baseline).
 rx_gain_control gain_ctrl (
    .clk(clk),
    .reset_n(reset_n),
@@ -247,21 +232,10 @@ rx_gain_control gain_ctrl (
    .data_q_in(adc_q_scaled),
    .valid_in(adc_valid_sync),
    .gain_shift(host_gain_shift),
-    // AGC configuration
-    .agc_enable(host_agc_enable),
-    .agc_target(host_agc_target),
-    .agc_attack(host_agc_attack),
-    .agc_decay(host_agc_decay),
-    .agc_holdoff(host_agc_holdoff),
-    // Frame boundary from Doppler processor
-    .frame_boundary(doppler_frame_done),
-    // Outputs
    .data_i_out(gc_i),
    .data_q_out(gc_q),
    .valid_out(gc_valid),
-    .saturation_count(gc_saturation_count),
-    .peak_magnitude(gc_peak_magnitude),
-    .current_gain(gc_current_gain)
+    .saturation_count(gc_saturation_count)
 );

 // 3. Dual Chirp Memory Loader
@@ -292,8 +266,7 @@ end
 // sample_addr_wire removed — was unused implicit wire (synthesis warning)

 // 4. CRITICAL: Reference Chirp Latency Buffer
-// This aligns reference data with FFT output (3187 cycle delay)
-// TODO: verify empirically during hardware bring-up with correlation test
+// This aligns reference data with FFT output (2159 cycle delay)
 wire [15:0] delayed_ref_i, delayed_ref_q;
 wire mem_ready_delayed;

@@ -309,10 +282,11 @@ latency_buffer #(
    .valid_out(mem_ready_delayed)
 );

-// Assign delayed reference signals (single pair — chirp_memory_loader_param
-// selects long/short reference upstream via use_long_chirp)
-assign ref_chirp_real = delayed_ref_i;
-assign ref_chirp_imag = delayed_ref_q;
+// Assign delayed reference signals
+assign long_chirp_real = delayed_ref_i;
+assign long_chirp_imag = delayed_ref_q;
+assign short_chirp_real = delayed_ref_i;
+assign short_chirp_imag = delayed_ref_q;

 // 5. Dual Chirp Matched Filter

@@ -336,8 +310,10 @@ matched_filter_multi_segment mf_dual (
    .mc_new_chirp(mc_new_chirp),
    .mc_new_elevation(mc_new_elevation),
    .mc_new_azimuth(mc_new_azimuth),
-	 .ref_chirp_real(delayed_ref_i),       // From latency buffer (long or short ref)
-    .ref_chirp_imag(delayed_ref_q),
+	 .long_chirp_real(delayed_ref_i),      // From latency buffer
+    .long_chirp_imag(delayed_ref_q),
+    .short_chirp_real(delayed_ref_i),     // Same for short chirp
+    .short_chirp_imag(delayed_ref_q),
    .segment_request(segment_request),
    .mem_request(mem_request),
 	 .sample_addr_out(sample_addr_from_chain),
@@ -498,9 +474,4 @@ assign dbg_adc_i     = adc_i_scaled;
 assign dbg_adc_q     = adc_q_scaled;
 assign dbg_adc_valid = adc_valid_sync;

-// ========== AGC STATUS OUTPUTS ==========
-assign agc_saturation_count = gc_saturation_count;
-assign agc_peak_magnitude   = gc_peak_magnitude;
-assign agc_current_gain     = gc_current_gain;
-
 endmodule
@@ -125,13 +125,7 @@ module radar_system_top (
    output wire [5:0] dbg_range_bin,
    
    // System status
-    output wire [3:0] system_status,
-
-    // FPGA→STM32 GPIO outputs (DIG_5..DIG_7 on 50T board)
-    // Used by STM32 outer AGC loop to read saturation state without USB polling.
-    output wire gpio_dig5,          // DIG_5 (H11→PD13): AGC saturation flag (1=clipping detected)
-    output wire gpio_dig6,          // DIG_6 (G12→PD14): reserved (tied low)
-    output wire gpio_dig7           // DIG_7 (H12→PD15): reserved (tied low)
+    output wire [3:0] system_status
 );

 // ============================================================================
@@ -193,11 +187,6 @@ wire [15:0] rx_dbg_adc_i;
 wire [15:0] rx_dbg_adc_q;
 wire        rx_dbg_adc_valid;

-// AGC status from receiver (for status readback and GPIO)
-wire [7:0]  rx_agc_saturation_count;
-wire [7:0]  rx_agc_peak_magnitude;
-wire [3:0]  rx_agc_current_gain;
-
 // Data packing for USB
 wire [31:0] usb_range_profile;
 wire usb_range_valid;
@@ -270,13 +259,6 @@ reg        host_cfar_enable;      // Opcode 0x25: 1=CFAR, 0=simple threshold
 reg        host_mti_enable;       // Opcode 0x26: 1=MTI active, 0=pass-through
 reg [2:0]  host_dc_notch_width;   // Opcode 0x27: DC notch ±width bins (0=off, 1..7)

-// AGC configuration registers (host-configurable via USB, opcodes 0x28-0x2C)
-reg        host_agc_enable;       // Opcode 0x28: 0=manual gain, 1=auto AGC
-reg [7:0]  host_agc_target;       // Opcode 0x29: target peak magnitude (default 200)
-reg [3:0]  host_agc_attack;       // Opcode 0x2A: gain-down step on clipping (default 1)
-reg [3:0]  host_agc_decay;        // Opcode 0x2B: gain-up step when weak (default 1)
-reg [3:0]  host_agc_holdoff;      // Opcode 0x2C: frames to wait before gain-up (default 4)
-
 // Board bring-up self-test registers (opcode 0x30 trigger, 0x31 readback)
 reg        host_self_test_trigger;  // Opcode 0x30: self-clearing pulse
 wire       self_test_busy;
@@ -536,12 +518,6 @@ radar_receiver_final rx_inst (
    .host_chirps_per_elev(host_chirps_per_elev),
    // Fix 3: digital gain control
    .host_gain_shift(host_gain_shift),
-    // AGC configuration (opcodes 0x28-0x2C)
-    .host_agc_enable(host_agc_enable),
-    .host_agc_target(host_agc_target),
-    .host_agc_attack(host_agc_attack),
-    .host_agc_decay(host_agc_decay),
-    .host_agc_holdoff(host_agc_holdoff),
    // STM32 toggle signals for RX mode controller (mode 00 pass-through).
    // These are the raw GPIO inputs — the RX mode controller's edge detectors
    // (inside radar_mode_controller) handle debouncing/edge detection.
@@ -556,11 +532,7 @@ radar_receiver_final rx_inst (
    // ADC debug tap (for self-test / bring-up)
    .dbg_adc_i(rx_dbg_adc_i),
    .dbg_adc_q(rx_dbg_adc_q),
-    .dbg_adc_valid(rx_dbg_adc_valid),
-    // AGC status outputs
-    .agc_saturation_count(rx_agc_saturation_count),
-    .agc_peak_magnitude(rx_agc_peak_magnitude),
-    .agc_current_gain(rx_agc_current_gain)
+    .dbg_adc_valid(rx_dbg_adc_valid)
 );

 // ============================================================================
@@ -772,13 +744,7 @@ if (USB_MODE == 0) begin : gen_ft601
        // Self-test status readback
        .status_self_test_flags(self_test_flags_latched),
        .status_self_test_detail(self_test_detail_latched),
-        .status_self_test_busy(self_test_busy),
-
-        // AGC status readback
-        .status_agc_current_gain(rx_agc_current_gain),
-        .status_agc_peak_magnitude(rx_agc_peak_magnitude),
-        .status_agc_saturation_count(rx_agc_saturation_count),
-        .status_agc_enable(host_agc_enable)
+        .status_self_test_busy(self_test_busy)
    );

    // FT2232H ports unused in FT601 mode — tie off
@@ -839,13 +805,7 @@ end else begin : gen_ft2232h
        // Self-test status readback
        .status_self_test_flags(self_test_flags_latched),
        .status_self_test_detail(self_test_detail_latched),
-        .status_self_test_busy(self_test_busy),
-
-        // AGC status readback
-        .status_agc_current_gain(rx_agc_current_gain),
-        .status_agc_peak_magnitude(rx_agc_peak_magnitude),
-        .status_agc_saturation_count(rx_agc_saturation_count),
-        .status_agc_enable(host_agc_enable)
+        .status_self_test_busy(self_test_busy)
    );

    // FT601 ports unused in FT2232H mode — tie off
@@ -932,12 +892,6 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
        // Ground clutter removal defaults (disabled — backward-compatible)
        host_mti_enable         <= 1'b0;      // MTI off
        host_dc_notch_width     <= 3'd0;      // DC notch off
-        // AGC defaults (disabled — backward-compatible with manual gain)
-        host_agc_enable         <= 1'b0;      // AGC off (manual gain)
-        host_agc_target         <= 8'd200;    // Target peak magnitude
-        host_agc_attack         <= 4'd1;      // 1-step gain-down on clipping
-        host_agc_decay          <= 4'd1;      // 1-step gain-up when weak
-        host_agc_holdoff        <= 4'd4;      // 4 frames before gain-up
        // Self-test defaults
        host_self_test_trigger  <= 1'b0;      // Self-test idle
    end else begin
@@ -982,12 +936,6 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                // Ground clutter removal opcodes
                8'h26: host_mti_enable         <= usb_cmd_value[0];
                8'h27: host_dc_notch_width     <= usb_cmd_value[2:0];
-                // AGC configuration opcodes
-                8'h28: host_agc_enable         <= usb_cmd_value[0];
-                8'h29: host_agc_target         <= usb_cmd_value[7:0];
-                8'h2A: host_agc_attack         <= usb_cmd_value[3:0];
-                8'h2B: host_agc_decay          <= usb_cmd_value[3:0];
-                8'h2C: host_agc_holdoff        <= usb_cmd_value[3:0];
                // Board bring-up self-test opcodes
                8'h30: host_self_test_trigger  <= 1'b1;  // Trigger self-test
                8'h31: host_status_request     <= 1'b1;  // Self-test readback (status alias)
@@ -1030,16 +978,6 @@ end

 assign system_status = status_reg;

-// ============================================================================
-// FPGA→STM32 GPIO OUTPUTS (DIG_5, DIG_6, DIG_7)
-// ============================================================================
-// DIG_5: AGC saturation flag — high when per-frame saturation_count > 0.
-//        STM32 reads PD13 to detect clipping and adjust ADAR1000 VGA gain.
-// DIG_6, DIG_7: Reserved (tied low for future use).
-assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
-assign gpio_dig6 = 1'b0;
-assign gpio_dig7 = 1'b0;
-
 // ============================================================================
 // DEBUG AND VERIFICATION
 // ============================================================================
@@ -76,12 +76,7 @@ module radar_system_top_50t (
    output wire ft_rd_n,              // Read strobe (active low)
    output wire ft_wr_n,              // Write strobe (active low)
    output wire ft_oe_n,              // Output enable / bus direction
-    output wire ft_siwu,              // Send Immediate / WakeUp
-
-    // ===== FPGA→STM32 GPIO (Bank 15: 3.3V) =====
-    output wire gpio_dig5,            // DIG_5 (H11→PD13): AGC saturation flag
-    output wire gpio_dig6,            // DIG_6 (G12→PD14): reserved
-    output wire gpio_dig7             // DIG_7 (H12→PD15): reserved
+    output wire ft_siwu               // Send Immediate / WakeUp
 );

    // ===== Tie-off wires for unconstrained FT601 inputs (inactive with USB_MODE=1) =====
@@ -212,12 +207,7 @@ module radar_system_top_50t (
        .dbg_doppler_valid      (dbg_doppler_valid_nc),
        .dbg_doppler_bin        (dbg_doppler_bin_nc),
        .dbg_range_bin          (dbg_range_bin_nc),
-        .system_status          (system_status_nc),
-
-        // ----- FPGA→STM32 GPIO (DIG_5..DIG_7) -----
-        .gpio_dig5              (gpio_dig5),
-        .gpio_dig6              (gpio_dig6),
-        .gpio_dig7              (gpio_dig7)
+        .system_status          (system_status_nc)
    );

 endmodule
@@ -253,68 +253,6 @@ run_lint_static() {
    fi
 }

-# ---------------------------------------------------------------------------
-# Helper: compile, run, and compare a matched-filter co-sim scenario
-#   run_mf_cosim <scenario_name> <define_flag>
-# ---------------------------------------------------------------------------
-run_mf_cosim() {
-    local name="$1"
-    local define="$2"
-    local vvp="tb/tb_mf_cosim_${name}.vvp"
-    local scenario_lower="$name"
-
-    printf "  %-45s " "MF Co-Sim ($name)"
-
-    # Compile — build command as string to handle optional define
-    local cmd="iverilog -g2001 -DSIMULATION"
-    if [[ -n "$define" ]]; then
-        cmd="$cmd $define"
-    fi
-    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
-
-    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
-        echo -e "${RED}COMPILE FAIL${NC}"
-        ERRORS="$ERRORS\n  MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
-        FAIL=$((FAIL + 1))
-        return
-    fi
-
-    # Run TB
-    local output
-    output=$(timeout 120 vvp "$vvp" 2>&1) || true
-    rm -f "$vvp"
-
-    # Check TB internal pass/fail
-    local tb_fail
-    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
-    if [[ "$tb_fail" -gt 0 ]]; then
-        echo -e "${RED}FAIL${NC} (TB internal failure)"
-        ERRORS="$ERRORS\n  MF Co-Sim ($name): TB internal failure"
-        FAIL=$((FAIL + 1))
-        return
-    fi
-
-    # Run Python compare
-    if command -v python3 >/dev/null 2>&1; then
-        local compare_out
-        local compare_rc=0
-        compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
-        if [[ "$compare_rc" -ne 0 ]]; then
-            echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
-            ERRORS="$ERRORS\n  MF Co-Sim ($name): Python compare failed"
-            FAIL=$((FAIL + 1))
-            return
-        fi
-    else
-        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
-        SKIP=$((SKIP + 1))
-        return
-    fi
-
-    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
-    PASS=$((PASS + 1))
-}
-
 # ---------------------------------------------------------------------------
 # Helper: compile and run a single testbench
 #   run_test <name> <vvp_path> <iverilog_args...>
@@ -465,27 +403,31 @@ run_test "DDC Chain (NCO→CIC→FIR)" \
    tb/tb_ddc_cosim.v ddc_400m.v nco_400m_enhanced.v \
    cic_decimator_4x_enhanced.v fir_lowpass.v cdc_modules.v

-# Real-data co-simulation: committed golden hex vs RTL (exact match required).
-# These catch architecture mismatches (e.g. 32-pt → dual 16-pt Doppler FFT)
-# that self-blessing golden-generate/compare tests cannot detect.
-run_test "Doppler Real-Data (ADI CN0566, exact match)" \
-    tb/tb_doppler_realdata.vvp \
-    tb/tb_doppler_realdata.v doppler_processor.v xfft_16.v fft_engine.v
-
-run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
-    tb/tb_fullchain_realdata.vvp \
-    tb/tb_fullchain_realdata.v range_bin_decimator.v \
-    doppler_processor.v xfft_16.v fft_engine.v
-
 if [[ "$QUICK" -eq 0 ]]; then
-    # NOTE: The "Receiver golden generate/compare" pair was REMOVED because
-    # it was self-blessing: both passes ran the same RTL with the same
-    # deterministic stimulus, so the test always passed regardless of bugs.
-    # Real co-sim coverage is provided by:
-    #   - tb_doppler_realdata.v  (committed Python golden hex, exact match)
-    #   - tb_fullchain_realdata.v (committed Python golden hex, exact match)
-    # A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
-    # planned as a replacement (Phase C of CI test plan).
+    # Golden generate
+    run_test "Receiver (golden generate)" \
+        tb/tb_rx_golden_reg.vvp \
+        -DGOLDEN_GENERATE \
+        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        rx_gain_control.v mti_canceller.v
+
+    # Golden compare
+    run_test "Receiver (golden compare)" \
+        tb/tb_rx_compare_reg.vvp \
+        tb/tb_radar_receiver_final.v radar_receiver_final.v \
+        radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
+        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        chirp_memory_loader_param.v latency_buffer.v \
+        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+        rx_gain_control.v mti_canceller.v

    # Full system top (monitoring-only, legacy)
    run_test "System Top (radar_system_tb)" \
@@ -515,28 +457,12 @@ if [[ "$QUICK" -eq 0 ]]; then
        usb_data_interface.v edge_detector.v radar_mode_controller.v \
        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
 else
-    echo "  (skipped system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 2))
+    echo "  (skipped receiver golden + system top + E2E — use without --quick)"
+    SKIP=$((SKIP + 4))
 fi

 echo ""

-# ===========================================================================
-# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
-# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
-# against committed Python golden CSV files. In SIMULATION mode, thresholds
-# are generous (behavioral vs fixed-point twiddles differ) — validates
-# state machine mechanics, output count, and energy sanity.
-# ===========================================================================
-echo "--- PHASE 2b: Matched Filter Co-Sim ---"
-
-run_mf_cosim "chirp"   ""
-run_mf_cosim "dc"      "-DSCENARIO_DC"
-run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
-run_mf_cosim "tone5"   "-DSCENARIO_TONE5"
-
-echo ""
-
 # ===========================================================================
 # PHASE 3: UNIT TESTS — Signal Processing
 # ===========================================================================
@@ -3,32 +3,19 @@
 /**
 * rx_gain_control.v
 *
- * Digital gain control with optional per-frame automatic gain control (AGC)
- * for the receive path. Placed between DDC output and matched filter input.
+ * Host-configurable digital gain control for the receive path.
+ * Placed between DDC output (ddc_input_interface) and matched filter input.
 *
- * Manual mode (agc_enable=0):
- *   - Uses host_gain_shift directly (backward-compatible, no behavioral change)
+ * Features:
+ *   - Bidirectional power-of-2 gain shift (arithmetic shift)
 *   - gain_shift[3]   = direction: 0 = left shift (amplify), 1 = right shift (attenuate)
 *   - gain_shift[2:0] = amount: 0..7 bits
- *   - Symmetric saturation to ±32767 on overflow
+ *   - Symmetric saturation to ±32767 on overflow (left shift only)
+ *   - Saturation counter: 8-bit, counts samples that clipped (wraps at 255)
+ *   - 1-cycle latency, valid-in/valid-out pipeline
+ *   - Zero-overhead pass-through when gain_shift == 0
 *
- * AGC mode (agc_enable=1):
- *   - Per-frame automatic gain adjustment based on peak/saturation metrics
- *   - Internal signed gain: -7 (max attenuation) to +7 (max amplification)
- *   - On frame_boundary:
- *       * If saturation detected: gain -= agc_attack (fast, immediate)
- *       * Else if peak < target after holdoff frames: gain += agc_decay (slow)
- *       * Else: hold current gain
- *   - host_gain_shift serves as initial gain when AGC first enabled
- *
- * Status outputs (for readback via status_words):
- *   - current_gain[3:0]: effective gain_shift encoding (manual or AGC)
- *   - peak_magnitude[7:0]: per-frame peak |sample| (upper 8 bits of 15-bit value)
- *   - saturation_count[7:0]: per-frame clipped sample count (capped at 255)
- *
- * Timing: 1-cycle data latency, valid-in/valid-out pipeline.
- *
- * Insertion point in radar_receiver_final.v:
+ * Intended insertion point in radar_receiver_final.v:
 *   ddc_input_interface → rx_gain_control → matched_filter_multi_segment
 */

@@ -41,75 +28,27 @@ module rx_gain_control (
    input  wire signed [15:0] data_q_in,
    input  wire               valid_in,

-    // Host gain configuration (from USB command opcode 0x16)
-    // [3]=direction: 0=amplify (left shift), 1=attenuate (right shift)
-    // [2:0]=shift amount: 0..7 bits. Default 0x00 = pass-through.
-    // In AGC mode: serves as initial gain on AGC enable transition.
+    // Gain configuration (from host via USB command)
+    // [3]   = direction: 0=amplify (left shift), 1=attenuate (right shift)
+    // [2:0] = shift amount: 0..7 bits
    input  wire [3:0]  gain_shift,

-    // AGC configuration inputs (from host via USB, opcodes 0x28-0x2C)
-    input  wire        agc_enable,     // 0x28: 0=manual gain, 1=auto AGC
-    input  wire [7:0]  agc_target,     // 0x29: target peak magnitude (unsigned, default 200)
-    input  wire [3:0]  agc_attack,     // 0x2A: attenuation step on clipping (default 1)
-    input  wire [3:0]  agc_decay,      // 0x2B: amplification step when weak (default 1)
-    input  wire [3:0]  agc_holdoff,    // 0x2C: frames to wait before gain-up (default 4)
-
-    // Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
-    input  wire        frame_boundary,
-
    // Data output (to matched filter)
    output reg  signed [15:0] data_i_out,
    output reg  signed [15:0] data_q_out,
    output reg                valid_out,

-    // Diagnostics / status readback
-    output reg  [7:0]  saturation_count,  // Per-frame clipped sample count (capped at 255)
-    output reg  [7:0]  peak_magnitude,    // Per-frame peak |sample| (upper 8 bits of 15-bit)
-    output reg  [3:0]  current_gain       // Current effective gain_shift (for status readback)
+    // Diagnostics
+    output reg  [7:0]  saturation_count  // Number of clipped samples (wraps at 255)
 );

-// =========================================================================
-// INTERNAL AGC STATE
-// =========================================================================
+// Decompose gain_shift
+wire       shift_right = gain_shift[3];
+wire [2:0] shift_amt   = gain_shift[2:0];

-// Signed internal gain: -7 (max attenuation) to +7 (max amplification)
-// Stored as 4-bit signed (range -8..+7, clamped to -7..+7)
-reg signed [3:0] agc_gain;
-
-// Holdoff counter: counts frames without saturation before allowing gain-up
-reg [3:0] holdoff_counter;
-
-// Per-frame accumulators (running, reset on frame_boundary)
-reg [7:0]  frame_sat_count;    // Clipped samples this frame
-reg [14:0] frame_peak;         // Peak |sample| this frame (15-bit unsigned)
-
-// Previous AGC enable state (for detecting 0→1 transition)
-reg agc_enable_prev;
-
-// Combinational helpers for inclusive frame-boundary snapshot
-// (used when valid_in and frame_boundary coincide)
-reg wire_frame_sat_incr;
-reg wire_frame_peak_update;
-
-// =========================================================================
-// EFFECTIVE GAIN SELECTION
-// =========================================================================
-
-// Convert between signed internal gain and the gain_shift[3:0] encoding.
-//   gain_shift[3]=0, [2:0]=N → amplify by N bits (internal gain = +N)
-//   gain_shift[3]=1, [2:0]=N → attenuate by N bits (internal gain = -N)
-
-// Effective gain_shift used for the actual shift operation
-wire [3:0] effective_gain;
-assign effective_gain = agc_enable ? current_gain : gain_shift;
-
-// Decompose effective gain for shift logic
-wire       shift_right = effective_gain[3];
-wire [2:0] shift_amt   = effective_gain[2:0];
-
-// =========================================================================
-// COMBINATIONAL SHIFT + SATURATION
-// =========================================================================
+// -------------------------------------------------------------------------
+// Combinational shift + saturation
+// -------------------------------------------------------------------------
 // Use wider intermediates to detect overflow on left shift.
 // 24 bits is enough: 16 + 7 shift = 23 significant bits max.

@@ -130,153 +69,26 @@ wire signed [15:0] sat_i = overflow_i ? (shifted_i[23] ? -16'sd32768 : 16'sd3276
 wire signed [15:0] sat_q = overflow_q ? (shifted_q[23] ? -16'sd32768 : 16'sd32767)
                                      : shifted_q[15:0];

-// =========================================================================
-// PEAK MAGNITUDE TRACKING (combinational)
-// =========================================================================
-// Absolute value of signed 16-bit: flip sign bit if negative.
-// Result is 15-bit unsigned [0, 32767]. (We ignore -32768 → 32767 edge case.)
-wire [14:0] abs_i = data_i_in[15] ? (~data_i_in[14:0] + 15'd1) : data_i_in[14:0];
-wire [14:0] abs_q = data_q_in[15] ? (~data_q_in[14:0] + 15'd1) : data_q_in[14:0];
-wire [14:0] max_iq = (abs_i > abs_q) ? abs_i : abs_q;
-
-// =========================================================================
-// SIGNED GAIN ↔ GAIN_SHIFT ENCODING CONVERSION
-// =========================================================================
-// Convert signed agc_gain to gain_shift[3:0] encoding
-function [3:0] signed_to_encoding;
-    input signed [3:0] g;
-    begin
-        if (g >= 0)
-            signed_to_encoding = {1'b0, g[2:0]};       // amplify
-        else
-            signed_to_encoding = {1'b1, (~g[2:0]) + 3'd1}; // attenuate: -g
-    end
-endfunction
-
-// Convert gain_shift[3:0] encoding to signed gain
-function signed [3:0] encoding_to_signed;
-    input [3:0] enc;
-    begin
-        if (enc[3] == 1'b0)
-            encoding_to_signed = {1'b0, enc[2:0]};     // +0..+7
-        else
-            encoding_to_signed = -$signed({1'b0, enc[2:0]}); // -1..-7
-    end
-endfunction
-
-// =========================================================================
-// CLAMPING HELPER
-// =========================================================================
-// Clamp a wider signed value to [-7, +7]
-function signed [3:0] clamp_gain;
-    input signed [4:0] val;  // 5-bit to handle overflow from add
-    begin
-        if (val > 5'sd7)
-            clamp_gain = 4'sd7;
-        else if (val < -5'sd7)
-            clamp_gain = -4'sd7;
-        else
-            clamp_gain = val[3:0];
-    end
-endfunction
-
-// =========================================================================
-// REGISTERED OUTPUT + AGC STATE MACHINE
-// =========================================================================
+// -------------------------------------------------------------------------
+// Registered output stage (1-cycle latency)
+// -------------------------------------------------------------------------
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
-        // Data path
        data_i_out       <= 16'sd0;
        data_q_out       <= 16'sd0;
        valid_out        <= 1'b0;
-        // Status outputs
        saturation_count <= 8'd0;
-        peak_magnitude   <= 8'd0;
-        current_gain     <= 4'd0;
-        // AGC internal state
-        agc_gain         <= 4'sd0;
-        holdoff_counter  <= 4'd0;
-        frame_sat_count  <= 8'd0;
-        frame_peak       <= 15'd0;
-        agc_enable_prev  <= 1'b0;
    end else begin
-        // Track AGC enable transitions
-        agc_enable_prev <= agc_enable;
-
-        // Compute inclusive metrics: if valid_in fires this cycle,
-        // include current sample in the snapshot taken at frame_boundary.
-        // This avoids losing the last sample when valid_in and
-        // frame_boundary coincide (NBA last-write-wins would otherwise
-        // snapshot stale values then reset, dropping the sample entirely).
-        wire_frame_sat_incr = (valid_in && (overflow_i || overflow_q)
-                               && (frame_sat_count != 8'hFF));
-        wire_frame_peak_update = (valid_in && (max_iq > frame_peak));
-
-        // ---- Data pipeline (1-cycle latency) ----
        valid_out <= valid_in;
+
        if (valid_in) begin
            data_i_out <= sat_i;
            data_q_out <= sat_q;

-            // Per-frame saturation counting
-            if ((overflow_i || overflow_q) && (frame_sat_count != 8'hFF))
-                frame_sat_count <= frame_sat_count + 8'd1;
-
-            // Per-frame peak tracking (pre-gain, measures input signal level)
-            if (max_iq > frame_peak)
-                frame_peak <= max_iq;
+            // Count clipped samples (either channel clipping counts as 1)
+            if ((overflow_i || overflow_q) && (saturation_count != 8'hFF))
+                saturation_count <= saturation_count + 8'd1;
        end
-
-        // ---- Frame boundary: AGC update + metric snapshot ----
-        if (frame_boundary) begin
-            // Snapshot per-frame metrics INCLUDING current sample if valid_in
-            saturation_count <= wire_frame_sat_incr
-                                ? (frame_sat_count + 8'd1)
-                                : frame_sat_count;
-            peak_magnitude   <= wire_frame_peak_update
-                                ? max_iq[14:7]
-                                : frame_peak[14:7];
-
-            // Reset per-frame accumulators for next frame
-            frame_sat_count <= 8'd0;
-            frame_peak      <= 15'd0;
-
-            if (agc_enable) begin
-                // AGC auto-adjustment at frame boundary
-                // Use inclusive counts/peaks (accounting for simultaneous valid_in)
-                if (wire_frame_sat_incr || frame_sat_count > 8'd0) begin
-                    // Clipping detected: reduce gain immediately (attack)
-                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) -
-                                           $signed({1'b0, agc_attack}));
-                    holdoff_counter <= agc_holdoff;  // Reset holdoff
-                end else if ((wire_frame_peak_update ? max_iq[14:7] : frame_peak[14:7])
-                             < agc_target) begin
-                    // Signal too weak: increase gain after holdoff expires
-                    if (holdoff_counter == 4'd0) begin
-                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) +
-                                               $signed({1'b0, agc_decay}));
-                    end else begin
-                        holdoff_counter <= holdoff_counter - 4'd1;
-                    end
-                end else begin
-                    // Signal in good range, no saturation: hold gain
-                    // Reset holdoff so next weak frame has to wait again
-                    holdoff_counter <= agc_holdoff;
-                end
-            end
-        end
-
-        // ---- AGC enable transition: initialize from host gain ----
-        if (agc_enable && !agc_enable_prev) begin
-            agc_gain        <= encoding_to_signed(gain_shift);
-            holdoff_counter <= agc_holdoff;
-        end
-
-        // ---- Update current_gain output ----
-        if (agc_enable)
-            current_gain <= signed_to_encoding(agc_gain);
-        else
-            current_gain <= gain_shift;
    end
 end

@@ -120,10 +120,9 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]

 # ---- Run implementation steps ----
 opt_design -directive Explore
-place_design -directive ExtraNetDelay_high
-phys_opt_design -directive AggressiveExplore
-route_design -directive AggressiveExplore
+place_design -directive Explore
 phys_opt_design -directive AggressiveExplore
+route_design -directive Explore
 phys_opt_design -directive AggressiveExplore

 set impl_elapsed [expr {[clock seconds] - $impl_start}]
@@ -29,7 +29,7 @@ import sys
 # Add this directory to path for imports
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))

-from fpga_model import SignalChain
+from fpga_model import SignalChain, sign_extend


 # =============================================================================
@@ -93,7 +93,7 @@ SCENARIOS = {
 def load_adc_hex(filepath):
    """Load 8-bit unsigned ADC samples from hex file."""
    samples = []
-    with open(filepath) as f:
+    with open(filepath, 'r') as f:
        for line in f:
            line = line.strip()
            if not line or line.startswith('//'):
@@ -106,8 +106,8 @@ def load_rtl_csv(filepath):
    """Load RTL baseband output CSV (sample_idx, baseband_i, baseband_q)."""
    bb_i = []
    bb_q = []
-    with open(filepath) as f:
-        f.readline()  # Skip header
+    with open(filepath, 'r') as f:
+        header = f.readline()  # Skip header
        for line in f:
            line = line.strip()
            if not line:
@@ -125,6 +125,7 @@ def run_python_model(adc_samples):
    because the RTL testbench captures the FIR output directly
    (baseband_i_reg <= fir_i_out in ddc_400m.v).
    """
+    print("  Running Python model...")

    chain = SignalChain()
    result = chain.process_adc_block(adc_samples)
@@ -134,6 +135,7 @@ def run_python_model(adc_samples):
    bb_i = result['fir_i_raw']
    bb_q = result['fir_q_raw']

+    print(f"  Python model: {len(bb_i)} baseband I, {len(bb_q)} baseband Q outputs")
    return bb_i, bb_q


@@ -143,7 +145,7 @@ def compute_rms_error(a, b):
        raise ValueError(f"Length mismatch: {len(a)} vs {len(b)}")
    if len(a) == 0:
        return 0.0
-    sum_sq = sum((x - y) ** 2 for x, y in zip(a, b, strict=False))
+    sum_sq = sum((x - y) ** 2 for x, y in zip(a, b))
    return math.sqrt(sum_sq / len(a))


@@ -151,7 +153,7 @@ def compute_max_abs_error(a, b):
    """Compute maximum absolute error between two equal-length lists."""
    if len(a) != len(b) or len(a) == 0:
        return 0
-    return max(abs(x - y) for x, y in zip(a, b, strict=False))
+    return max(abs(x - y) for x, y in zip(a, b))


 def compute_correlation(a, b):
@@ -233,29 +235,44 @@ def compute_signal_stats(samples):
 def compare_scenario(scenario_name):
    """Run comparison for one scenario. Returns True if passed."""
    if scenario_name not in SCENARIOS:
+        print(f"ERROR: Unknown scenario '{scenario_name}'")
+        print(f"Available: {', '.join(SCENARIOS.keys())}")
        return False

    cfg = SCENARIOS[scenario_name]
    base_dir = os.path.dirname(os.path.abspath(__file__))

+    print("=" * 60)
+    print(f"Co-simulation Comparison: {cfg['description']}")
+    print(f"Scenario: {scenario_name}")
+    print("=" * 60)

    # ---- Load ADC data ----
    adc_path = os.path.join(base_dir, cfg['adc_hex'])
    if not os.path.exists(adc_path):
+        print(f"ERROR: ADC hex file not found: {adc_path}")
+        print("Run radar_scene.py first to generate test vectors.")
        return False
    adc_samples = load_adc_hex(adc_path)
+    print(f"\nADC samples loaded: {len(adc_samples)}")

    # ---- Load RTL output ----
    rtl_path = os.path.join(base_dir, cfg['rtl_csv'])
    if not os.path.exists(rtl_path):
+        print(f"ERROR: RTL CSV not found: {rtl_path}")
+        print("Run the RTL simulation first:")
+        print(f"  iverilog -g2001 -DSIMULATION -DSCENARIO_{scenario_name.upper()} ...")
        return False
    rtl_i, rtl_q = load_rtl_csv(rtl_path)
+    print(f"RTL outputs loaded: {len(rtl_i)} I, {len(rtl_q)} Q samples")

    # ---- Run Python model ----
    py_i, py_q = run_python_model(adc_samples)

    # ---- Length comparison ----
+    print(f"\nOutput lengths: RTL={len(rtl_i)}, Python={len(py_i)}")
    len_diff = abs(len(rtl_i) - len(py_i))
+    print(f"Length difference: {len_diff} samples")

    # ---- Signal statistics ----
    rtl_i_stats = compute_signal_stats(rtl_i)
@@ -263,10 +280,20 @@ def compare_scenario(scenario_name):
    py_i_stats = compute_signal_stats(py_i)
    py_q_stats = compute_signal_stats(py_q)

+    print(f"\nSignal Statistics:")
+    print(f"  RTL I: mean={rtl_i_stats['mean']:.1f}, rms={rtl_i_stats['rms']:.1f}, "
+          f"range=[{rtl_i_stats['min']}, {rtl_i_stats['max']}]")
+    print(f"  RTL Q: mean={rtl_q_stats['mean']:.1f}, rms={rtl_q_stats['rms']:.1f}, "
+          f"range=[{rtl_q_stats['min']}, {rtl_q_stats['max']}]")
+    print(f"  Py  I: mean={py_i_stats['mean']:.1f}, rms={py_i_stats['rms']:.1f}, "
+          f"range=[{py_i_stats['min']}, {py_i_stats['max']}]")
+    print(f"  Py  Q: mean={py_q_stats['mean']:.1f}, rms={py_q_stats['rms']:.1f}, "
+          f"range=[{py_q_stats['min']}, {py_q_stats['max']}]")

    # ---- Trim to common length ----
    common_len = min(len(rtl_i), len(py_i))
    if common_len < 10:
+        print(f"ERROR: Too few common samples ({common_len})")
        return False

    rtl_i_trim = rtl_i[:common_len]
@@ -275,14 +302,18 @@ def compare_scenario(scenario_name):
    py_q_trim = py_q[:common_len]

    # ---- Cross-correlation to find latency offset ----
-    lag_i, _corr_i = cross_correlate_lag(rtl_i_trim, py_i_trim,
+    print(f"\nLatency alignment (cross-correlation, max lag=±{MAX_LATENCY_DRIFT}):")
+    lag_i, corr_i = cross_correlate_lag(rtl_i_trim, py_i_trim,
                                        max_lag=MAX_LATENCY_DRIFT)
-    lag_q, _corr_q = cross_correlate_lag(rtl_q_trim, py_q_trim,
+    lag_q, corr_q = cross_correlate_lag(rtl_q_trim, py_q_trim,
                                        max_lag=MAX_LATENCY_DRIFT)
+    print(f"  I-channel: best lag={lag_i}, correlation={corr_i:.6f}")
+    print(f"  Q-channel: best lag={lag_q}, correlation={corr_q:.6f}")

    # ---- Apply latency correction ----
    best_lag = lag_i  # Use I-channel lag (should be same as Q)
    if abs(lag_i - lag_q) > 1:
+        print(f"  WARNING: I and Q latency offsets differ ({lag_i} vs {lag_q})")
        # Use the average
        best_lag = (lag_i + lag_q) // 2

@@ -310,20 +341,29 @@ def compare_scenario(scenario_name):
    aligned_py_i = aligned_py_i[:aligned_len]
    aligned_py_q = aligned_py_q[:aligned_len]

+    print(f"  Applied lag correction: {best_lag} samples")
+    print(f"  Aligned length: {aligned_len} samples")

    # ---- Error metrics (after alignment) ----
    rms_i = compute_rms_error(aligned_rtl_i, aligned_py_i)
    rms_q = compute_rms_error(aligned_rtl_q, aligned_py_q)
-    compute_max_abs_error(aligned_rtl_i, aligned_py_i)
-    compute_max_abs_error(aligned_rtl_q, aligned_py_q)
+    max_err_i = compute_max_abs_error(aligned_rtl_i, aligned_py_i)
+    max_err_q = compute_max_abs_error(aligned_rtl_q, aligned_py_q)
    corr_i_aligned = compute_correlation(aligned_rtl_i, aligned_py_i)
    corr_q_aligned = compute_correlation(aligned_rtl_q, aligned_py_q)

+    print(f"\nError Metrics (after alignment):")
+    print(f"  I-channel: RMS={rms_i:.2f} LSB, max={max_err_i} LSB, corr={corr_i_aligned:.6f}")
+    print(f"  Q-channel: RMS={rms_q:.2f} LSB, max={max_err_q} LSB, corr={corr_q_aligned:.6f}")

    # ---- First/last sample comparison ----
+    print(f"\nFirst 10 samples (after alignment):")
+    print(f"  {'idx':>4s}  {'RTL_I':>8s}  {'Py_I':>8s}  {'Err_I':>6s}  {'RTL_Q':>8s}  {'Py_Q':>8s}  {'Err_Q':>6s}")
    for k in range(min(10, aligned_len)):
        ei = aligned_rtl_i[k] - aligned_py_i[k]
        eq = aligned_rtl_q[k] - aligned_py_q[k]
+        print(f"  {k:4d}  {aligned_rtl_i[k]:8d}  {aligned_py_i[k]:8d}  {ei:6d}  "
+              f"{aligned_rtl_q[k]:8d}  {aligned_py_q[k]:8d}  {eq:6d}")

    # ---- Write detailed comparison CSV ----
    compare_csv_path = os.path.join(base_dir, f"compare_{scenario_name}.csv")
@@ -334,6 +374,7 @@ def compare_scenario(scenario_name):
            eq = aligned_rtl_q[k] - aligned_py_q[k]
            f.write(f"{k},{aligned_rtl_i[k]},{aligned_py_i[k]},{ei},"
                    f"{aligned_rtl_q[k]},{aligned_py_q[k]},{eq}\n")
+    print(f"\nDetailed comparison written to: {compare_csv_path}")

    # ---- Pass/Fail ----
    max_rms = cfg.get('max_rms', MAX_RMS_ERROR_LSB)
@@ -399,15 +440,22 @@ def compare_scenario(scenario_name):
                     f"|{best_lag}| <= {MAX_LATENCY_DRIFT}"))

    # ---- Report ----
+    print(f"\n{'─' * 60}")
+    print("PASS/FAIL Results:")
    all_pass = True
-    for _name, ok, _detail in results:
+    for name, ok, detail in results:
+        status = "PASS" if ok else "FAIL"
+        mark = "[PASS]" if ok else "[FAIL]"
+        print(f"  {mark} {name}: {detail}")
        if not ok:
            all_pass = False

+    print(f"\n{'=' * 60}")
    if all_pass:
-        pass
+        print(f"SCENARIO {scenario_name.upper()}: ALL CHECKS PASSED")
    else:
-        pass
+        print(f"SCENARIO {scenario_name.upper()}: SOME CHECKS FAILED")
+    print(f"{'=' * 60}")

    return all_pass

@@ -431,18 +479,25 @@ def main():
                        pass_count += 1
                    else:
                        overall_pass = False
+                    print()
                else:
-                    pass
+                    print(f"Skipping {name}: RTL CSV not found ({cfg['rtl_csv']})")

+            print("=" * 60)
+            print(f"OVERALL: {pass_count}/{run_count} scenarios passed")
            if overall_pass:
-                pass
+                print("ALL SCENARIOS PASSED")
            else:
-                pass
+                print("SOME SCENARIOS FAILED")
+            print("=" * 60)
            return 0 if overall_pass else 1
-        ok = compare_scenario(scenario)
+        else:
+            ok = compare_scenario(scenario)
+            return 0 if ok else 1
+    else:
+        # Default: DC
+        ok = compare_scenario('dc')
        return 0 if ok else 1
-    ok = compare_scenario('dc')
-    return 0 if ok else 1


 if __name__ == '__main__':
@@ -4085,3 +4085,4 @@ idx,rtl_i,py_i,err_i,rtl_q,py_q,err_q
 4083,21,20,1,-6,-6,0
 4084,20,21,-1,-6,-6,0
 4085,20,20,0,-5,-6,1
+4086,20,20,0,-5,-5,0
@@ -73,8 +73,8 @@ def load_doppler_csv(filepath):
    Returns dict: {rbin: [(dbin, i, q), ...]}
    """
    data = {}
-    with open(filepath) as f:
-        f.readline()  # Skip header
+    with open(filepath, 'r') as f:
+        header = f.readline()
        for line in f:
            line = line.strip()
            if not line:
@@ -117,7 +117,7 @@ def pearson_correlation(a, b):

 def magnitude_l1(i_arr, q_arr):
    """L1 magnitude: |I| + |Q|."""
-    return [abs(i) + abs(q) for i, q in zip(i_arr, q_arr, strict=False)]
+    return [abs(i) + abs(q) for i, q in zip(i_arr, q_arr)]


 def find_peak_bin(i_arr, q_arr):
@@ -143,7 +143,7 @@ def total_energy(data_dict):
    """Sum of I^2 + Q^2 across all range bins and Doppler bins."""
    total = 0
    for rbin in data_dict:
-        for (_dbin, i_val, q_val) in data_dict[rbin]:
+        for (dbin, i_val, q_val) in data_dict[rbin]:
            total += i_val * i_val + q_val * q_val
    return total

@@ -154,30 +154,44 @@ def total_energy(data_dict):

 def compare_scenario(name, config, base_dir):
    """Compare one Doppler scenario. Returns (passed, result_dict)."""
+    print(f"\n{'='*60}")
+    print(f"Scenario: {name} — {config['description']}")
+    print(f"{'='*60}")

    golden_path = os.path.join(base_dir, config['golden_csv'])
    rtl_path = os.path.join(base_dir, config['rtl_csv'])

    if not os.path.exists(golden_path):
+        print(f"  ERROR: Golden CSV not found: {golden_path}")
+        print(f"  Run: python3 gen_doppler_golden.py")
        return False, {}
    if not os.path.exists(rtl_path):
+        print(f"  ERROR: RTL CSV not found: {rtl_path}")
+        print(f"  Run the Verilog testbench first")
        return False, {}

    py_data = load_doppler_csv(golden_path)
    rtl_data = load_doppler_csv(rtl_path)

-    sorted(py_data.keys())
-    sorted(rtl_data.keys())
+    py_rbins = sorted(py_data.keys())
+    rtl_rbins = sorted(rtl_data.keys())

+    print(f"  Python: {len(py_rbins)} range bins, "
+          f"{sum(len(v) for v in py_data.values())} total samples")
+    print(f"  RTL:    {len(rtl_rbins)} range bins, "
+          f"{sum(len(v) for v in rtl_data.values())} total samples")

    # ---- Check 1: Both have data ----
    py_total = sum(len(v) for v in py_data.values())
    rtl_total = sum(len(v) for v in rtl_data.values())
    if py_total == 0 or rtl_total == 0:
+        print("  ERROR: One or both outputs are empty")
        return False, {}

    # ---- Check 2: Output count ----
    count_ok = (rtl_total == TOTAL_OUTPUTS)
+    print(f"\n  Output count: RTL={rtl_total}, expected={TOTAL_OUTPUTS} "
+          f"{'OK' if count_ok else 'MISMATCH'}")

    # ---- Check 3: Global energy ----
    py_energy = total_energy(py_data)
@@ -187,6 +201,10 @@ def compare_scenario(name, config, base_dir):
    else:
        energy_ratio = 1.0 if rtl_energy == 0 else float('inf')

+    print(f"\n  Global energy:")
+    print(f"    Python: {py_energy}")
+    print(f"    RTL:    {rtl_energy}")
+    print(f"    Ratio:  {energy_ratio:.4f}")

    # ---- Check 4: Per-range-bin analysis ----
    peak_agreements = 0
@@ -218,8 +236,8 @@ def compare_scenario(name, config, base_dir):
        i_correlations.append(corr_i)
        q_correlations.append(corr_q)

-        py_rbin_energy = sum(i*i + q*q for i, q in zip(py_i, py_q, strict=False))
-        rtl_rbin_energy = sum(i*i + q*q for i, q in zip(rtl_i, rtl_q, strict=False))
+        py_rbin_energy = sum(i*i + q*q for i, q in zip(py_i, py_q))
+        rtl_rbin_energy = sum(i*i + q*q for i, q in zip(rtl_i, rtl_q))

        peak_details.append({
            'rbin': rbin,
@@ -237,11 +255,20 @@ def compare_scenario(name, config, base_dir):
    avg_corr_i = sum(i_correlations) / len(i_correlations)
    avg_corr_q = sum(q_correlations) / len(q_correlations)

+    print(f"\n  Per-range-bin metrics:")
+    print(f"    Peak Doppler bin agreement (+/-1 within sub-frame): {peak_agreements}/{RANGE_BINS} "
+          f"({peak_agreement_frac:.0%})")
+    print(f"    Avg magnitude correlation: {avg_mag_corr:.4f}")
+    print(f"    Avg I-channel correlation: {avg_corr_i:.4f}")
+    print(f"    Avg Q-channel correlation: {avg_corr_q:.4f}")

    # Show top 5 range bins by Python energy
+    print(f"\n  Top 5 range bins by Python energy:")
    top_rbins = sorted(peak_details, key=lambda x: -x['py_energy'])[:5]
-    for _d in top_rbins:
-        pass
+    for d in top_rbins:
+        print(f"    rbin={d['rbin']:2d}: py_peak={d['py_peak']:2d}, "
+              f"rtl_peak={d['rtl_peak']:2d}, mag_corr={d['mag_corr']:.3f}, "
+              f"I_corr={d['corr_i']:.3f}, Q_corr={d['corr_q']:.3f}")

    # ---- Pass/Fail ----
    checks = []
@@ -264,8 +291,11 @@ def compare_scenario(name, config, base_dir):
        checks.append((f'High-energy rbin avg mag_corr >= {MAG_CORR_MIN:.2f} '
                        f'(actual={he_mag_corr:.3f})', he_ok))

+    print(f"\n  Pass/Fail Checks:")
    all_pass = True
-    for _check_name, passed in checks:
+    for check_name, passed in checks:
+        status = "PASS" if passed else "FAIL"
+        print(f"    [{status}] {check_name}")
        if not passed:
            all_pass = False

@@ -280,6 +310,7 @@ def compare_scenario(name, config, base_dir):
                f.write(f'{rbin},{dbin},{py_i[dbin]},{py_q[dbin]},'
                        f'{rtl_i[dbin]},{rtl_q[dbin]},'
                        f'{rtl_i[dbin]-py_i[dbin]},{rtl_q[dbin]-py_q[dbin]}\n')
+    print(f"\n  Detailed comparison: {compare_csv}")

    result = {
        'scenario': name,
@@ -302,15 +333,25 @@ def compare_scenario(name, config, base_dir):
 def main():
    base_dir = os.path.dirname(os.path.abspath(__file__))

-    arg = sys.argv[1].lower() if len(sys.argv) > 1 else 'stationary'
+    if len(sys.argv) > 1:
+        arg = sys.argv[1].lower()
+    else:
+        arg = 'stationary'

    if arg == 'all':
        run_scenarios = list(SCENARIOS.keys())
    elif arg in SCENARIOS:
        run_scenarios = [arg]
    else:
+        print(f"Unknown scenario: {arg}")
+        print(f"Valid: {', '.join(SCENARIOS.keys())}, all")
        sys.exit(1)

+    print("=" * 60)
+    print("Doppler Processor Co-Simulation Comparison")
+    print("RTL vs Python model (clean, no pipeline bug replication)")
+    print(f"Scenarios: {', '.join(run_scenarios)}")
+    print("=" * 60)

    results = []
    for name in run_scenarios:
@@ -318,20 +359,37 @@ def main():
        results.append((name, passed, result))

    # Summary
+    print(f"\n{'='*60}")
+    print("SUMMARY")
+    print(f"{'='*60}")

+    print(f"\n  {'Scenario':<15} {'Energy Ratio':>13} {'Mag Corr':>10} "
+          f"{'Peak Agree':>11} {'I Corr':>8} {'Q Corr':>8} {'Status':>8}")
+    print(f"  {'-'*15} {'-'*13} {'-'*10} {'-'*11} {'-'*8} {'-'*8} {'-'*8}")

    all_pass = True
-    for _name, passed, result in results:
+    for name, passed, result in results:
        if not result:
+            print(f"  {name:<15} {'ERROR':>13} {'—':>10} {'—':>11} "
+                  f"{'—':>8} {'—':>8} {'FAIL':>8}")
            all_pass = False
        else:
+            status = "PASS" if passed else "FAIL"
+            print(f"  {name:<15} {result['energy_ratio']:>13.4f} "
+                  f"{result['avg_mag_corr']:>10.4f} "
+                  f"{result['peak_agreement']:>10.0%} "
+                  f"{result['avg_corr_i']:>8.4f} "
+                  f"{result['avg_corr_q']:>8.4f} "
+                  f"{status:>8}")
            if not passed:
                all_pass = False

+    print()
    if all_pass:
-        pass
+        print("ALL TESTS PASSED")
    else:
-        pass
+        print("SOME TESTS FAILED")
+    print(f"{'='*60}")

    sys.exit(0 if all_pass else 1)

@@ -79,8 +79,8 @@ def load_csv(filepath):
    """Load CSV with columns (bin, out_i/range_profile_i, out_q/range_profile_q)."""
    vals_i = []
    vals_q = []
-    with open(filepath) as f:
-        f.readline()  # Skip header
+    with open(filepath, 'r') as f:
+        header = f.readline()
        for line in f:
            line = line.strip()
            if not line:
@@ -93,17 +93,17 @@ def load_csv(filepath):

 def magnitude_spectrum(vals_i, vals_q):
    """Compute magnitude = |I| + |Q| for each bin (L1 norm, matches RTL)."""
-    return [abs(i) + abs(q) for i, q in zip(vals_i, vals_q, strict=False)]
+    return [abs(i) + abs(q) for i, q in zip(vals_i, vals_q)]


 def magnitude_l2(vals_i, vals_q):
    """Compute magnitude = sqrt(I^2 + Q^2) for each bin."""
-    return [math.sqrt(i*i + q*q) for i, q in zip(vals_i, vals_q, strict=False)]
+    return [math.sqrt(i*i + q*q) for i, q in zip(vals_i, vals_q)]


 def total_energy(vals_i, vals_q):
    """Compute total energy (sum of I^2 + Q^2)."""
-    return sum(i*i + q*q for i, q in zip(vals_i, vals_q, strict=False))
+    return sum(i*i + q*q for i, q in zip(vals_i, vals_q))


 def rms_magnitude(vals_i, vals_q):
@@ -111,7 +111,7 @@ def rms_magnitude(vals_i, vals_q):
    n = len(vals_i)
    if n == 0:
        return 0.0
-    return math.sqrt(sum(i*i + q*q for i, q in zip(vals_i, vals_q, strict=False)) / n)
+    return math.sqrt(sum(i*i + q*q for i, q in zip(vals_i, vals_q)) / n)


 def pearson_correlation(a, b):
@@ -144,7 +144,7 @@ def find_peak(vals_i, vals_q):
 def top_n_peaks(mags, n=10):
    """Find the top-N peak bins by magnitude. Returns set of bin indices."""
    indexed = sorted(enumerate(mags), key=lambda x: -x[1])
-    return {idx for idx, _ in indexed[:n]}
+    return set(idx for idx, _ in indexed[:n])


 def spectral_peak_overlap(mags_a, mags_b, n=10):
@@ -163,20 +163,30 @@ def spectral_peak_overlap(mags_a, mags_b, n=10):

 def compare_scenario(scenario_name, config, base_dir):
    """Compare one scenario. Returns (pass/fail, result_dict)."""
+    print(f"\n{'='*60}")
+    print(f"Scenario: {scenario_name} — {config['description']}")
+    print(f"{'='*60}")

    golden_path = os.path.join(base_dir, config['golden_csv'])
    rtl_path = os.path.join(base_dir, config['rtl_csv'])

    if not os.path.exists(golden_path):
+        print(f"  ERROR: Golden CSV not found: {golden_path}")
+        print(f"  Run: python3 gen_mf_cosim_golden.py")
        return False, {}
    if not os.path.exists(rtl_path):
+        print(f"  ERROR: RTL CSV not found: {rtl_path}")
+        print(f"  Run the RTL testbench first")
        return False, {}

    py_i, py_q = load_csv(golden_path)
    rtl_i, rtl_q = load_csv(rtl_path)

+    print(f"  Python model: {len(py_i)} samples")
+    print(f"  RTL output:   {len(rtl_i)} samples")

    if len(py_i) != FFT_SIZE or len(rtl_i) != FFT_SIZE:
+        print(f"  ERROR: Expected {FFT_SIZE} samples from each")
        return False, {}

    # ---- Metric 1: Energy ----
@@ -195,17 +205,28 @@ def compare_scenario(scenario_name, config, base_dir):
        energy_ratio = float('inf') if py_energy == 0 else 0.0
        rms_ratio = float('inf') if py_rms == 0 else 0.0

+    print(f"\n  Energy:")
+    print(f"    Python total energy:  {py_energy}")
+    print(f"    RTL total energy:     {rtl_energy}")
+    print(f"    Energy ratio (RTL/Py): {energy_ratio:.4f}")
+    print(f"    Python RMS:           {py_rms:.2f}")
+    print(f"    RTL RMS:              {rtl_rms:.2f}")
+    print(f"    RMS ratio (RTL/Py):   {rms_ratio:.4f}")

    # ---- Metric 2: Peak location ----
-    py_peak_bin, _py_peak_mag = find_peak(py_i, py_q)
-    rtl_peak_bin, _rtl_peak_mag = find_peak(rtl_i, rtl_q)
+    py_peak_bin, py_peak_mag = find_peak(py_i, py_q)
+    rtl_peak_bin, rtl_peak_mag = find_peak(rtl_i, rtl_q)

+    print(f"\n  Peak location:")
+    print(f"    Python: bin={py_peak_bin}, mag={py_peak_mag}")
+    print(f"    RTL:    bin={rtl_peak_bin}, mag={rtl_peak_mag}")

    # ---- Metric 3: Magnitude spectrum correlation ----
    py_mag = magnitude_l2(py_i, py_q)
    rtl_mag = magnitude_l2(rtl_i, rtl_q)
    mag_corr = pearson_correlation(py_mag, rtl_mag)

+    print(f"\n  Magnitude spectrum correlation: {mag_corr:.6f}")

    # ---- Metric 4: Top-N peak overlap ----
    # Use L1 magnitudes for peak finding (matches RTL)
@@ -214,11 +235,16 @@ def compare_scenario(scenario_name, config, base_dir):
    peak_overlap_10 = spectral_peak_overlap(py_mag_l1, rtl_mag_l1, n=10)
    peak_overlap_20 = spectral_peak_overlap(py_mag_l1, rtl_mag_l1, n=20)

+    print(f"  Top-10 peak overlap:   {peak_overlap_10:.2%}")
+    print(f"  Top-20 peak overlap:   {peak_overlap_20:.2%}")

    # ---- Metric 5: I and Q channel correlation ----
    corr_i = pearson_correlation(py_i, rtl_i)
    corr_q = pearson_correlation(py_q, rtl_q)

+    print(f"\n  Channel correlation:")
+    print(f"    I-channel: {corr_i:.6f}")
+    print(f"    Q-channel: {corr_q:.6f}")

    # ---- Pass/Fail Decision ----
    # The SIMULATION branch uses floating-point twiddles ($cos/$sin) while
@@ -252,8 +278,11 @@ def compare_scenario(scenario_name, config, base_dir):
                    energy_ok))

    # Print checks
+    print(f"\n  Pass/Fail Checks:")
    all_pass = True
-    for _name, passed in checks:
+    for name, passed in checks:
+        status = "PASS" if passed else "FAIL"
+        print(f"    [{status}] {name}")
        if not passed:
            all_pass = False

@@ -281,6 +310,7 @@ def compare_scenario(scenario_name, config, base_dir):
            f.write(f'{k},{py_i[k]},{py_q[k]},{rtl_i[k]},{rtl_q[k]},'
                    f'{py_mag_l1[k]},{rtl_mag_l1[k]},'
                    f'{rtl_i[k]-py_i[k]},{rtl_q[k]-py_q[k]}\n')
+    print(f"\n  Detailed comparison: {compare_csv}")

    return all_pass, result

@@ -292,15 +322,25 @@ def compare_scenario(scenario_name, config, base_dir):
 def main():
    base_dir = os.path.dirname(os.path.abspath(__file__))

-    arg = sys.argv[1].lower() if len(sys.argv) > 1 else 'chirp'
+    if len(sys.argv) > 1:
+        arg = sys.argv[1].lower()
+    else:
+        arg = 'chirp'

    if arg == 'all':
        run_scenarios = list(SCENARIOS.keys())
    elif arg in SCENARIOS:
        run_scenarios = [arg]
    else:
+        print(f"Unknown scenario: {arg}")
+        print(f"Valid: {', '.join(SCENARIOS.keys())}, all")
        sys.exit(1)

+    print("=" * 60)
+    print("Matched Filter Co-Simulation Comparison")
+    print("RTL (synthesis branch) vs Python model (bit-accurate)")
+    print(f"Scenarios: {', '.join(run_scenarios)}")
+    print("=" * 60)

    results = []
    for name in run_scenarios:
@@ -308,20 +348,37 @@ def main():
        results.append((name, passed, result))

    # Summary
+    print(f"\n{'='*60}")
+    print("SUMMARY")
+    print(f"{'='*60}")

+    print(f"\n  {'Scenario':<12} {'Energy Ratio':>13} {'Mag Corr':>10} "
+          f"{'Peak Ovlp':>10} {'Py Peak':>8} {'RTL Peak':>9} {'Status':>8}")
+    print(f"  {'-'*12} {'-'*13} {'-'*10} {'-'*10} {'-'*8} {'-'*9} {'-'*8}")

    all_pass = True
-    for _name, passed, result in results:
+    for name, passed, result in results:
        if not result:
+            print(f"  {name:<12} {'ERROR':>13} {'—':>10} {'—':>10} "
+                  f"{'—':>8} {'—':>9} {'FAIL':>8}")
            all_pass = False
        else:
+            status = "PASS" if passed else "FAIL"
+            print(f"  {name:<12} {result['energy_ratio']:>13.4f} "
+                  f"{result['mag_corr']:>10.4f} "
+                  f"{result['peak_overlap_10']:>9.0%} "
+                  f"{result['py_peak_bin']:>8d} "
+                  f"{result['rtl_peak_bin']:>9d} "
+                  f"{status:>8}")
            if not passed:
                all_pass = False

+    print()
    if all_pass:
-        pass
+        print("ALL TESTS PASSED")
    else:
-        pass
+        print("SOME TESTS FAILED")
+    print(f"{'='*60}")

    sys.exit(0 if all_pass else 1)

@@ -19,6 +19,7 @@ Author: Phase 0.5 co-simulation suite for PLFM_RADAR
 """

 import os
+import struct

 # =============================================================================
 # Fixed-point utility functions
@@ -50,7 +51,7 @@ def saturate(value, bits):
    return value


-def arith_rshift(value, shift, _width=None):
+def arith_rshift(value, shift, width=None):
    """Arithmetic right shift. Python >> on signed int is already arithmetic."""
    return value >> shift

@@ -129,7 +130,10 @@ class NCO:
        raw_index = lut_address & 0x3F

        # RTL: lut_index = (quadrant[0] ^ quadrant[1]) ? ~lut_address[5:0] : lut_address[5:0]
-        lut_index = ~raw_index & 63 if quadrant & 1 ^ quadrant >> 1 & 1 else raw_index
+        if (quadrant & 1) ^ ((quadrant >> 1) & 1):
+            lut_index = (~raw_index) & 0x3F
+        else:
+            lut_index = raw_index

        return quadrant, lut_index

@@ -172,7 +176,7 @@ class NCO:
            # OLD phase_accum_reg (the value from the PREVIOUS call).
            # We stored self.phase_accum_reg at the start of this call as the
            # value from last cycle. So:
-            # phase_with_offset computed below from OLD values
+            pass  # phase_with_offset computed below from OLD values

        # Compute all NBA assignments from OLD state:
        # Save old state for NBA evaluation
@@ -192,13 +196,18 @@ class NCO:

        if phase_valid:
            # Stage 1 NBA: phase_accum_reg <= phase_accumulator (old value)
-            _new_phase_accum_reg = (self.phase_accumulator - ftw) & 0xFFFFFFFF
+            new_phase_accum_reg = (self.phase_accumulator - ftw) & 0xFFFFFFFF  # old accum before add
            # Wait - let me re-derive. The Verilog is:
+            #   phase_accumulator <= phase_accumulator + frequency_tuning_word;
+            #   phase_accum_reg   <= phase_accumulator;  // OLD value (NBA)
+            #   phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0};  // OLD phase_accum_reg
+            # Since all are NBA (<=), they all read the values from BEFORE this edge.
+            # So: new_phase_accumulator = old_phase_accumulator + ftw
+            #     new_phase_accum_reg   = old_phase_accumulator
+            #     new_phase_with_offset = old_phase_accum_reg + offset
            old_phase_accumulator = (self.phase_accumulator - ftw) & 0xFFFFFFFF  # reconstruct
            self.phase_accum_reg = old_phase_accumulator
-            self.phase_with_offset = (
-                old_phase_accum_reg + ((phase_offset << 16) & 0xFFFFFFFF)
-            ) & 0xFFFFFFFF
+            self.phase_with_offset = (old_phase_accum_reg + ((phase_offset << 16) & 0xFFFFFFFF)) & 0xFFFFFFFF
            # phase_accumulator was already updated above

        # ---- Stage 3a: Register LUT address + quadrant ----
@@ -599,14 +608,8 @@ class FIRFilter:
        if (old_valid_pipe >> 0) & 1:
            for i in range(16):
                # Sign-extend products to ACCUM_WIDTH
-                a = sign_extend(
-                    mult_results[2 * i] & ((1 << self.PRODUCT_WIDTH) - 1),
-                    self.PRODUCT_WIDTH,
-                )
-                b = sign_extend(
-                    mult_results[2 * i + 1] & ((1 << self.PRODUCT_WIDTH) - 1),
-                    self.PRODUCT_WIDTH,
-                )
+                a = sign_extend(mult_results[2*i] & ((1 << self.PRODUCT_WIDTH) - 1), self.PRODUCT_WIDTH)
+                b = sign_extend(mult_results[2*i+1] & ((1 << self.PRODUCT_WIDTH) - 1), self.PRODUCT_WIDTH)
                self.add_l0[i] = a + b

        # ---- Stage 2 (Level 1): 8 pairwise sums ----
@@ -695,6 +698,7 @@ class DDCInputInterface:
        if old_valid_sync:
            ddc_i = sign_extend(ddc_i_18 & 0x3FFFF, 18)
            ddc_q = sign_extend(ddc_q_18 & 0x3FFFF, 18)
+            # adc_i = ddc_i[17:2] + ddc_i[1]  (rounding)
            trunc_i = (ddc_i >> 2) & 0xFFFF  # bits [17:2]
            round_i = (ddc_i >> 1) & 1       # bit [1]
            trunc_q = (ddc_q >> 2) & 0xFFFF
@@ -720,7 +724,7 @@ def load_twiddle_rom(filepath=None):
        filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')

    values = []
-    with open(filepath) as f:
+    with open(filepath, 'r') as f:
        for line in f:
            line = line.strip()
            if not line or line.startswith('//'):
@@ -748,11 +752,12 @@ def _twiddle_lookup(k, n, cos_rom):

    if k == 0:
        return cos_rom[0], 0
-    if k == n4:
+    elif k == n4:
        return 0, cos_rom[0]
-    if k < n4:
+    elif k < n4:
        return cos_rom[k], cos_rom[n4 - k]
-    return sign_extend((-cos_rom[n2 - k]) & 0xFFFF, 16), cos_rom[k - n4]
+    else:
+        return sign_extend((-cos_rom[n2 - k]) & 0xFFFF, 16), cos_rom[k - n4]


 class FFTEngine:
@@ -807,6 +812,7 @@ class FFTEngine:
        # COMPUTE: LOG2N stages of butterflies
        for stage in range(log2n):
            half = 1 << stage
+            span = half << 1
            tw_stride = (n >> 1) >> stage

            for bfly in range(n // 2):
@@ -827,9 +833,11 @@ class FFTEngine:

                # Multiply (49-bit products)
                if not inverse:
+                    # Forward: t = b * (cos + j*sin)
                    prod_re = b_re * tw_cos + b_im * tw_sin
                    prod_im = b_im * tw_cos - b_re * tw_sin
                else:
+                    # Inverse: t = b * (cos - j*sin)
                    prod_re = b_re * tw_cos - b_im * tw_sin
                    prod_im = b_im * tw_cos + b_re * tw_sin

@@ -908,9 +916,10 @@ class FreqMatchedFilter:
            # Saturation check
            if rounded > 0x3FFF8000:
                return 0x7FFF
-            if rounded < -0x3FFF8000:
+            elif rounded < -0x3FFF8000:
                return sign_extend(0x8000, 16)
-            return sign_extend((rounded >> 15) & 0xFFFF, 16)
+            else:
+                return sign_extend((rounded >> 15) & 0xFFFF, 16)

        out_re = round_sat_extract(real_sum)
        out_im = round_sat_extract(imag_sum)
@@ -1045,6 +1054,7 @@ class RangeBinDecimator:
                out_im.append(best_im)

            elif mode == 2:
+                # Averaging: sum >> 4
                sum_re = 0
                sum_im = 0
                for s in range(df):
@@ -1334,48 +1344,66 @@ def _self_test():
    """Quick sanity checks for each module."""
    import math

+    print("=" * 60)
+    print("FPGA Model Self-Test")
+    print("=" * 60)

    # --- NCO test ---
+    print("\n--- NCO Test ---")
    nco = NCO()
    ftw = 0x4CCCCCCD  # 120 MHz at 400 MSPS
    # Run 20 cycles to fill pipeline
    results = []
-    for _ in range(20):
+    for i in range(20):
        s, c, ready = nco.step(ftw)
        if ready:
            results.append((s, c))

    if results:
+        print(f"  First valid output: sin={results[0][0]}, cos={results[0][1]}")
+        print(f"  Got {len(results)} valid outputs from 20 cycles")
        # Check quadrature: sin^2 + cos^2 should be approximately 32767^2
        s, c = results[-1]
        mag_sq = s * s + c * c
        expected = 32767 * 32767
-        abs(mag_sq - expected) / expected * 100
+        error_pct = abs(mag_sq - expected) / expected * 100
+        print(f"  Quadrature check: sin^2+cos^2={mag_sq}, expected~{expected}, error={error_pct:.2f}%")
+    print("  NCO: OK")

    # --- Mixer test ---
+    print("\n--- Mixer Test ---")
    mixer = Mixer()
    # Test with mid-scale ADC (128) and known cos/sin
-    for _ in range(5):
-        _mi, _mq, _mv = mixer.step(128, 0x7FFF, 0, True, True)
+    for i in range(5):
+        mi, mq, mv = mixer.step(128, 0x7FFF, 0, True, True)
+    print(f"  Mixer with adc=128, cos=max, sin=0: I={mi}, Q={mq}, valid={mv}")
+    print("  Mixer: OK")

    # --- CIC test ---
+    print("\n--- CIC Test ---")
    cic = CICDecimator()
    dc_val = sign_extend(0x1000, 18)  # Small positive DC
    out_count = 0
-    for _ in range(100):
-        _, valid = cic.step(dc_val, True)
+    for i in range(100):
+        out, valid = cic.step(dc_val, True)
        if valid:
            out_count += 1
+    print(f"  CIC: {out_count} outputs from 100 inputs (expect ~25 with 4x decimation + pipeline)")
+    print("  CIC: OK")

    # --- FIR test ---
+    print("\n--- FIR Test ---")
    fir = FIRFilter()
    out_count = 0
-    for _ in range(50):
-        _out, valid = fir.step(1000, True)
+    for i in range(50):
+        out, valid = fir.step(1000, True)
        if valid:
            out_count += 1
+    print(f"  FIR: {out_count} outputs from 50 inputs (expect ~43 with 7-cycle latency)")
+    print("  FIR: OK")

    # --- FFT test ---
+    print("\n--- FFT Test (1024-pt) ---")
    try:
        fft = FFTEngine(n=1024)
        # Single tone at bin 10
@@ -1387,28 +1415,43 @@ def _self_test():
        out_re, out_im = fft.compute(in_re, in_im, inverse=False)
        # Find peak bin
        max_mag = 0
+        peak_bin = 0
        for i in range(512):
            mag = abs(out_re[i]) + abs(out_im[i])
            if mag > max_mag:
                max_mag = mag
+                peak_bin = i
+        print(f"  FFT peak at bin {peak_bin} (expected 10), magnitude={max_mag}")
        # IFFT roundtrip
-        rt_re, _rt_im = fft.compute(out_re, out_im, inverse=True)
-        max(abs(rt_re[i] - in_re[i]) for i in range(1024))
+        rt_re, rt_im = fft.compute(out_re, out_im, inverse=True)
+        max_err = max(abs(rt_re[i] - in_re[i]) for i in range(1024))
+        print(f"  FFT->IFFT roundtrip max error: {max_err} LSBs")
+        print("  FFT: OK")
    except FileNotFoundError:
-        pass
+        print("  FFT: SKIPPED (twiddle file not found)")

    # --- Conjugate multiply test ---
+    print("\n--- Conjugate Multiply Test ---")
    # (1+j0) * conj(1+j0) = 1+j0
    # In Q15: 32767 * 32767 -> should get close to 32767
-    _r, _m = FreqMatchedFilter.conjugate_multiply_sample(0x7FFF, 0, 0x7FFF, 0)
+    r, m = FreqMatchedFilter.conjugate_multiply_sample(0x7FFF, 0, 0x7FFF, 0)
+    print(f"  (32767+j0) * conj(32767+j0) = {r}+j{m} (expect ~32767+j0)")
    # (0+j32767) * conj(0+j32767) = (0+j32767)(0-j32767) = 32767^2 -> ~32767
-    _r2, _m2 = FreqMatchedFilter.conjugate_multiply_sample(0, 0x7FFF, 0, 0x7FFF)
+    r2, m2 = FreqMatchedFilter.conjugate_multiply_sample(0, 0x7FFF, 0, 0x7FFF)
+    print(f"  (0+j32767) * conj(0+j32767) = {r2}+j{m2} (expect ~32767+j0)")
+    print("  Conjugate Multiply: OK")

    # --- Range decimator test ---
+    print("\n--- Range Bin Decimator Test ---")
    test_re = list(range(1024))
    test_im = [0] * 1024
    out_re, out_im = RangeBinDecimator.decimate(test_re, test_im, mode=0)
+    print(f"  Mode 0 (center): first 5 bins = {out_re[:5]} (expect [8, 24, 40, 56, 72])")
+    print("  Range Decimator: OK")

+    print("\n" + "=" * 60)
+    print("ALL SELF-TESTS PASSED")
+    print("=" * 60)


 if __name__ == '__main__':
@@ -82,8 +82,8 @@ def generate_full_long_chirp():
    for n in range(LONG_CHIRP_SAMPLES):
        t = n / FS_SYS
        phase = math.pi * chirp_rate * t * t
-        re_val = round(Q15_MAX * SCALE * math.cos(phase))
-        im_val = round(Q15_MAX * SCALE * math.sin(phase))
+        re_val = int(round(Q15_MAX * SCALE * math.cos(phase)))
+        im_val = int(round(Q15_MAX * SCALE * math.sin(phase)))
        chirp_i.append(max(-32768, min(32767, re_val)))
        chirp_q.append(max(-32768, min(32767, im_val)))

@@ -105,8 +105,8 @@ def generate_short_chirp():
    for n in range(SHORT_CHIRP_SAMPLES):
        t = n / FS_SYS
        phase = math.pi * chirp_rate * t * t
-        re_val = round(Q15_MAX * SCALE * math.cos(phase))
-        im_val = round(Q15_MAX * SCALE * math.sin(phase))
+        re_val = int(round(Q15_MAX * SCALE * math.cos(phase)))
+        im_val = int(round(Q15_MAX * SCALE * math.sin(phase)))
        chirp_i.append(max(-32768, min(32767, re_val)))
        chirp_q.append(max(-32768, min(32767, im_val)))

@@ -126,17 +126,40 @@ def write_mem_file(filename, values):
    with open(path, 'w') as f:
        for v in values:
            f.write(to_hex16(v) + '\n')
+    print(f"  Wrote {filename}: {len(values)} entries")


 def main():
+    print("=" * 60)
+    print("AERIS-10 Chirp .mem File Generator")
+    print("=" * 60)
+    print()
+    print(f"Parameters:")
+    print(f"  CHIRP_BW         = {CHIRP_BW/1e6:.1f} MHz")
+    print(f"  FS_SYS           = {FS_SYS/1e6:.1f} MHz")
+    print(f"  T_LONG_CHIRP     = {T_LONG_CHIRP*1e6:.1f} us")
+    print(f"  T_SHORT_CHIRP    = {T_SHORT_CHIRP*1e6:.1f} us")
+    print(f"  LONG_CHIRP_SAMPLES = {LONG_CHIRP_SAMPLES}")
+    print(f"  SHORT_CHIRP_SAMPLES = {SHORT_CHIRP_SAMPLES}")
+    print(f"  FFT_SIZE         = {FFT_SIZE}")
+    print(f"  Chirp rate (long)  = {CHIRP_BW/T_LONG_CHIRP:.3e} Hz/s")
+    print(f"  Chirp rate (short) = {CHIRP_BW/T_SHORT_CHIRP:.3e} Hz/s")
+    print(f"  Q15 scale        = {SCALE}")
+    print()

    # ---- Long chirp ----
+    print("Generating full long chirp (3000 samples)...")
    long_i, long_q = generate_full_long_chirp()

    # Verify first sample matches generate_reference_chirp_q15() from radar_scene.py
    # (which only generates the first 1024 samples)
+    print(f"  Sample[0]:    I={long_i[0]:6d}  Q={long_q[0]:6d}")
+    print(f"  Sample[1023]: I={long_i[1023]:6d}  Q={long_q[1023]:6d}")
+    print(f"  Sample[2999]: I={long_i[2999]:6d}  Q={long_q[2999]:6d}")

    # Segment into 4 x 1024 blocks
+    print()
+    print("Segmenting into 4 x 1024 blocks...")
    for seg in range(LONG_SEGMENTS):
        start = seg * FFT_SIZE
        end = start + FFT_SIZE
@@ -154,18 +177,27 @@ def main():
                seg_i.append(0)
                seg_q.append(0)

-        FFT_SIZE - valid_count
+        zero_count = FFT_SIZE - valid_count
+        print(f"  Seg {seg}: indices [{start}:{end-1}], "
+              f"valid={valid_count}, zeros={zero_count}")

        write_mem_file(f"long_chirp_seg{seg}_i.mem", seg_i)
        write_mem_file(f"long_chirp_seg{seg}_q.mem", seg_q)

    # ---- Short chirp ----
+    print()
+    print("Generating short chirp (50 samples)...")
    short_i, short_q = generate_short_chirp()
+    print(f"  Sample[0]:  I={short_i[0]:6d}  Q={short_q[0]:6d}")
+    print(f"  Sample[49]: I={short_i[49]:6d}  Q={short_q[49]:6d}")

    write_mem_file("short_chirp_i.mem", short_i)
    write_mem_file("short_chirp_q.mem", short_q)

    # ---- Verification summary ----
+    print()
+    print("=" * 60)
+    print("Verification:")

    # Cross-check seg0 against radar_scene.py generate_reference_chirp_q15()
    # That function generates exactly the first 1024 samples of the chirp
@@ -174,30 +206,39 @@ def main():
    for n in range(FFT_SIZE):
        t = n / FS_SYS
        phase = math.pi * chirp_rate * t * t
-        expected_i = max(-32768, min(32767, round(Q15_MAX * SCALE * math.cos(phase))))
-        expected_q = max(-32768, min(32767, round(Q15_MAX * SCALE * math.sin(phase))))
+        expected_i = max(-32768, min(32767, int(round(Q15_MAX * SCALE * math.cos(phase)))))
+        expected_q = max(-32768, min(32767, int(round(Q15_MAX * SCALE * math.sin(phase)))))
        if long_i[n] != expected_i or long_q[n] != expected_q:
            mismatches += 1

    if mismatches == 0:
-        pass
+        print(f"  [PASS] Seg0 matches radar_scene.py generate_reference_chirp_q15()")
    else:
+        print(f"  [FAIL] Seg0 has {mismatches} mismatches vs generate_reference_chirp_q15()")
        return 1

    # Check magnitude envelope
-    max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
+    max_mag = max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q))
+    print(f"  Max magnitude: {max_mag:.1f} (expected ~{Q15_MAX * SCALE:.1f})")
+    print(f"  Magnitude ratio: {max_mag / (Q15_MAX * SCALE):.6f}")

    # Check seg3 zero padding
    seg3_i_path = os.path.join(MEM_DIR, 'long_chirp_seg3_i.mem')
-    with open(seg3_i_path) as f:
-        seg3_lines = [line.strip() for line in f if line.strip()]
-    nonzero_seg3 = sum(1 for line in seg3_lines if line != '0000')
+    with open(seg3_i_path, 'r') as f:
+        seg3_lines = [l.strip() for l in f if l.strip()]
+    nonzero_seg3 = sum(1 for l in seg3_lines if l != '0000')
+    print(f"  Seg3 non-zero entries: {nonzero_seg3}/{len(seg3_lines)} "
+          f"(expected 0 since chirp ends at sample 2999)")

    if nonzero_seg3 == 0:
-        pass
+        print(f"  [PASS] Seg3 is all zeros (chirp 3000 samples < seg3 start 3072)")
    else:
-        pass
+        print(f"  [WARN] Seg3 has {nonzero_seg3} non-zero entries")

+    print()
+    print(f"Generated 10 .mem files in {os.path.abspath(MEM_DIR)}")
+    print("Run validate_mem_files.py to do full validation.")
+    print("=" * 60)

    return 0

@@ -18,13 +18,14 @@ Usage:
 Author: Phase 0.5 Doppler co-simulation suite for PLFM_RADAR
 """

+import math
 import os
 import sys

 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))

 from fpga_model import (
-    DopplerProcessor
+    DopplerProcessor, sign_extend, HAMMING_WINDOW
 )
 from radar_scene import Target, generate_doppler_frame

@@ -51,6 +52,7 @@ def write_hex_32bit(filepath, samples):
        for (i_val, q_val) in samples:
            packed = ((q_val & 0xFFFF) << 16) | (i_val & 0xFFFF)
            f.write(f"{packed:08X}\n")
+    print(f"  Wrote {len(samples)} packed samples to {filepath}")


 def write_csv(filepath, headers, *columns):
@@ -60,6 +62,7 @@ def write_csv(filepath, headers, *columns):
        for i in range(len(columns[0])):
            row = ','.join(str(col[i]) for col in columns)
            f.write(row + '\n')
+    print(f"  Wrote {len(columns[0])} rows to {filepath}")


 def write_hex_16bit(filepath, data):
@@ -116,19 +119,22 @@ SCENARIOS = {

 def generate_scenario(name, targets, description, base_dir):
    """Generate input hex + golden output for one scenario."""
+    print(f"\n{'='*60}")
+    print(f"Scenario: {name} — {description}")
+    print(f"Model: CLEAN (dual 16-pt FFT)")
+    print(f"{'='*60}")

    # Generate Doppler frame (32 chirps x 64 range bins)
    frame_i, frame_q = generate_doppler_frame(targets, seed=42)

+    print(f"  Generated frame: {len(frame_i)} chirps x {len(frame_i[0])} range bins")

    # ---- Write input hex file (packed 32-bit: {Q, I}) ----
    # RTL expects data streamed chirp-by-chirp: chirp0[rb0..rb63], chirp1[rb0..rb63], ...
    packed_samples = []
    for chirp in range(CHIRPS_PER_FRAME):
-        packed_samples.extend(
-            (frame_i[chirp][rb], frame_q[chirp][rb])
-            for rb in range(RANGE_BINS)
-        )
+        for rb in range(RANGE_BINS):
+            packed_samples.append((frame_i[chirp][rb], frame_q[chirp][rb]))

    input_hex = os.path.join(base_dir, f"doppler_input_{name}.hex")
    write_hex_32bit(input_hex, packed_samples)
@@ -137,6 +143,8 @@ def generate_scenario(name, targets, description, base_dir):
    dp = DopplerProcessor()
    doppler_i, doppler_q = dp.process_frame(frame_i, frame_q)

+    print(f"  Doppler output: {len(doppler_i)} range bins x "
+          f"{len(doppler_i[0])} doppler bins (2 sub-frames x {DOPPLER_FFT_SIZE})")

    # ---- Write golden output CSV ----
    # Format: range_bin, doppler_bin, out_i, out_q
@@ -161,9 +169,10 @@ def generate_scenario(name, targets, description, base_dir):

    # ---- Write golden hex (for optional RTL $readmemh comparison) ----
    golden_hex = os.path.join(base_dir, f"doppler_golden_py_{name}.hex")
-    write_hex_32bit(golden_hex, list(zip(flat_i, flat_q, strict=False)))
+    write_hex_32bit(golden_hex, list(zip(flat_i, flat_q)))

    # ---- Find peak per range bin ----
+    print(f"\n  Peak Doppler bins per range bin (top 5 by magnitude):")
    peak_info = []
    for rbin in range(RANGE_BINS):
        mags = [abs(doppler_i[rbin][d]) + abs(doppler_q[rbin][d])
@@ -174,11 +183,13 @@ def generate_scenario(name, targets, description, base_dir):

    # Sort by magnitude descending, show top 5
    peak_info.sort(key=lambda x: -x[2])
-    for rbin, dbin, _mag in peak_info[:5]:
-        doppler_i[rbin][dbin]
-        doppler_q[rbin][dbin]
-        dbin // DOPPLER_FFT_SIZE
-        dbin % DOPPLER_FFT_SIZE
+    for rbin, dbin, mag in peak_info[:5]:
+        i_val = doppler_i[rbin][dbin]
+        q_val = doppler_q[rbin][dbin]
+        sf = dbin // DOPPLER_FFT_SIZE
+        bin_in_sf = dbin % DOPPLER_FFT_SIZE
+        print(f"    rbin={rbin:2d}, dbin={dbin:2d} (sf{sf}:{bin_in_sf:2d}), mag={mag:6d}, "
+              f"I={i_val:6d}, Q={q_val:6d}")

    return {
        'name': name,
@@ -190,6 +201,10 @@ def generate_scenario(name, targets, description, base_dir):
 def main():
    base_dir = os.path.dirname(os.path.abspath(__file__))

+    print("=" * 60)
+    print("Doppler Processor Co-Sim Golden Reference Generator")
+    print(f"Architecture: dual {DOPPLER_FFT_SIZE}-pt FFT ({DOPPLER_TOTAL_BINS} total bins)")
+    print("=" * 60)

    scenarios_to_run = list(SCENARIOS.keys())

@@ -207,9 +222,17 @@ def main():
        r = generate_scenario(name, targets, description, base_dir)
        results.append(r)

-    for _ in results:
-        pass
+    print(f"\n{'='*60}")
+    print("Summary:")
+    print(f"{'='*60}")
+    for r in results:
+        print(f"  {r['name']:<15s} top peak: "
+              f"rbin={r['peak_info'][0][0]}, dbin={r['peak_info'][0][1]}, "
+              f"mag={r['peak_info'][0][2]}")

+    print(f"\nGenerated {len(results)} scenarios.")
+    print(f"Files written to: {base_dir}")
+    print("=" * 60)


 if __name__ == '__main__':
@@ -25,8 +25,8 @@ import sys
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))

 from fpga_model import (
-    MatchedFilterChain,
-    sign_extend, saturate
+    FFTEngine, FreqMatchedFilter, MatchedFilterChain,
+    RangeBinDecimator, sign_extend, saturate
 )


@@ -36,7 +36,7 @@ FFT_SIZE = 1024
 def load_hex_16bit(filepath):
    """Load 16-bit hex file (one value per line, with optional // comments)."""
    values = []
-    with open(filepath) as f:
+    with open(filepath, 'r') as f:
        for line in f:
            line = line.strip()
            if not line or line.startswith('//'):
@@ -75,6 +75,7 @@ def generate_case(case_name, sig_i, sig_q, ref_i, ref_q, description, outdir,

    Returns dict with case info and results.
    """
+    print(f"\n--- {case_name}: {description} ---")

    assert len(sig_i) == FFT_SIZE, f"sig_i length {len(sig_i)} != {FFT_SIZE}"
    assert len(sig_q) == FFT_SIZE
@@ -87,6 +88,8 @@ def generate_case(case_name, sig_i, sig_q, ref_i, ref_q, description, outdir,
        write_hex_16bit(os.path.join(outdir, f"mf_sig_{case_name}_q.hex"), sig_q)
        write_hex_16bit(os.path.join(outdir, f"mf_ref_{case_name}_i.hex"), ref_i)
        write_hex_16bit(os.path.join(outdir, f"mf_ref_{case_name}_q.hex"), ref_q)
+        print(f"  Wrote input hex: mf_sig_{case_name}_{{i,q}}.hex, "
+              f"mf_ref_{case_name}_{{i,q}}.hex")

    # Run through bit-accurate Python model
    mf = MatchedFilterChain(fft_size=FFT_SIZE)
@@ -101,6 +104,9 @@ def generate_case(case_name, sig_i, sig_q, ref_i, ref_q, description, outdir,
            peak_mag = mag
            peak_bin = k

+    print(f"  Output: {len(out_i)} samples")
+    print(f"  Peak bin: {peak_bin}, magnitude: {peak_mag}")
+    print(f"  Peak I={out_i[peak_bin]}, Q={out_q[peak_bin]}")

    # Save golden output hex
    write_hex_16bit(os.path.join(outdir, f"mf_golden_py_i_{case_name}.hex"), out_i)
@@ -129,6 +135,10 @@ def generate_case(case_name, sig_i, sig_q, ref_i, ref_q, description, outdir,
 def main():
    base_dir = os.path.dirname(os.path.abspath(__file__))

+    print("=" * 60)
+    print("Matched Filter Co-Sim Golden Reference Generator")
+    print("Using bit-accurate Python model (fpga_model.py)")
+    print("=" * 60)

    results = []

@@ -148,7 +158,8 @@ def main():
                          base_dir)
        results.append(r)
    else:
-        pass
+        print("\nWARNING: bb_mf_test / ref_chirp hex files not found.")
+        print("Run radar_scene.py first.")

    # ---- Case 2: DC autocorrelation ----
    dc_val = 0x1000  # 4096
@@ -180,8 +191,8 @@ def main():
    sig_q = []
    for n in range(FFT_SIZE):
        angle = 2.0 * math.pi * k * n / FFT_SIZE
-        sig_i.append(saturate(round(amp * math.cos(angle)), 16))
-        sig_q.append(saturate(round(amp * math.sin(angle)), 16))
+        sig_i.append(saturate(int(round(amp * math.cos(angle))), 16))
+        sig_q.append(saturate(int(round(amp * math.sin(angle))), 16))
    ref_i = list(sig_i)
    ref_q = list(sig_q)
    r = generate_case("tone5", sig_i, sig_q, ref_i, ref_q,
@@ -190,9 +201,16 @@ def main():
    results.append(r)

    # ---- Summary ----
-    for _ in results:
-        pass
+    print("\n" + "=" * 60)
+    print("Summary:")
+    print("=" * 60)
+    for r in results:
+        print(f"  {r['case_name']:10s}: peak at bin {r['peak_bin']}, "
+              f"mag={r['peak_mag']}, I={r['peak_i']}, Q={r['peak_q']}")

+    print(f"\nGenerated {len(results)} golden reference cases.")
+    print("Files written to:", base_dir)
+    print("=" * 60)


 if __name__ == '__main__':
@@ -5,7 +5,7 @@ gen_multiseg_golden.py
 Generate golden reference data for matched_filter_multi_segment co-simulation.

 Tests the overlap-save segmented convolution wrapper:
-  - Long chirp: 3072 samples (4 segments x 1024, with 128-sample overlap)
+  - Long chirp: 3072 samples (4 segments × 1024, with 128-sample overlap)
  - Short chirp: 50 samples zero-padded to 1024 (1 segment)

 The matched_filter_processing_chain is already verified bit-perfect.
@@ -208,6 +208,7 @@ def generate_long_chirp_test():
    input_buffer_i = [0] * BUFFER_SIZE
    input_buffer_q = [0] * BUFFER_SIZE
    buffer_write_ptr = 0
+    current_segment = 0
    input_idx = 0
    chirp_samples_collected = 0

@@ -218,8 +219,7 @@ def generate_long_chirp_test():
        if seg == 0:
            buffer_write_ptr = 0
        else:
-            # Overlap-save: copy
-            # buffer[SEGMENT_ADVANCE:SEGMENT_ADVANCE+OVERLAP] -> buffer[0:OVERLAP]
+            # Overlap-save: copy buffer[SEGMENT_ADVANCE:SEGMENT_ADVANCE+OVERLAP] -> buffer[0:OVERLAP]
            for i in range(OVERLAP_SAMPLES):
                input_buffer_i[i] = input_buffer_i[i + SEGMENT_ADVANCE]
                input_buffer_q[i] = input_buffer_q[i + SEGMENT_ADVANCE]
@@ -234,6 +234,7 @@ def generate_long_chirp_test():
                # In radar_receiver_final.v, the DDC output is sign-extended:
                #   .ddc_i({{2{adc_i_scaled[15]}}, adc_i_scaled})
                # So 16-bit -> 18-bit sign-extend -> then multi_segment does:
+                #   ddc_i[17:2] + ddc_i[1]
                # For sign-extended 18-bit from 16-bit:
                #   ddc_i[17:2] = original 16-bit value (since bits [17:16] = sign extension)
                #   ddc_i[1] = bit 1 of original value
@@ -276,6 +277,9 @@ def generate_long_chirp_test():
        out_re, out_im = mf_chain.process(seg_data_i, seg_data_q, ref_i, ref_q)
        segment_results.append((out_re, out_im))

+        print(f"  Segment {seg}: collected {buffer_write_ptr} buffer samples, "
+              f"total chirp samples = {chirp_samples_collected}, "
+              f"input_idx = {input_idx}")

    # Write hex files for the testbench
    out_dir = os.path.dirname(os.path.abspath(__file__))
@@ -313,6 +317,7 @@ def generate_long_chirp_test():
            for b in range(1024):
                f.write(f'{seg},{b},{out_re[b]},{out_im[b]}\n')

+    print(f"\n  Written {LONG_SEGMENTS * 1024} golden samples to {csv_path}")

    return TOTAL_SAMPLES, LONG_SEGMENTS, segment_results

@@ -337,9 +342,8 @@ def generate_short_chirp_test():
        input_q.append(saturate(val_q, 16))

    # Zero-pad to 1024 (as RTL does in ST_ZERO_PAD)
-    # Note: padding computed here for documentation; actual buffer uses buf_i/buf_q below
-    _padded_i = list(input_i) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
-    _padded_q = list(input_q) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
+    padded_i = list(input_i) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
+    padded_q = list(input_q) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)

    # The buffer truncation: ddc_i[17:2] + ddc_i[1]
    # For data already 16-bit sign-extended to 18: result is (val >> 2) + bit1
@@ -376,6 +380,7 @@ def generate_short_chirp_test():
    # Write hex files
    out_dir = os.path.dirname(os.path.abspath(__file__))

+    # Input (18-bit)
    all_input_i_18 = []
    all_input_q_18 = []
    for n in range(SHORT_SAMPLES):
@@ -397,12 +402,19 @@ def generate_short_chirp_test():
        for b in range(1024):
            f.write(f'{b},{out_re[b]},{out_im[b]}\n')

+    print(f"  Written 1024 short chirp golden samples to {csv_path}")
    return out_re, out_im


 if __name__ == '__main__':
+    print("=" * 60)
+    print("Multi-Segment Matched Filter Golden Reference Generator")
+    print("=" * 60)

+    print("\n--- Long Chirp (4 segments, overlap-save) ---")
    total_samples, num_segs, seg_results = generate_long_chirp_test()
+    print(f"  Total input samples: {total_samples}")
+    print(f"  Segments: {num_segs}")

    for seg in range(num_segs):
        out_re, out_im = seg_results[seg]
@@ -414,7 +426,9 @@ if __name__ == '__main__':
            if mag > max_mag:
                max_mag = mag
                peak_bin = b
+        print(f"  Seg {seg}: peak at bin {peak_bin}, magnitude {max_mag}")

+    print("\n--- Short Chirp (1 segment, zero-padded) ---")
    short_re, short_im = generate_short_chirp_test()
    max_mag = 0
    peak_bin = 0
@@ -423,3 +437,8 @@ if __name__ == '__main__':
        if mag > max_mag:
            max_mag = mag
            peak_bin = b
+    print(f"  Short chirp: peak at bin {peak_bin}, magnitude {max_mag}")
+
+    print("\n" + "=" * 60)
+    print("ALL GOLDEN FILES GENERATED")
+    print("=" * 60)
@@ -21,6 +21,7 @@ Author: Phase 0.5 co-simulation suite for PLFM_RADAR

 import math
 import os
+import struct


 # =============================================================================
@@ -155,7 +156,7 @@ def generate_if_chirp(n_samples, chirp_bw=CHIRP_BW, f_if=F_IF, fs=FS_ADC):
        t = n / fs
        # Instantaneous frequency: f_if - chirp_bw/2 + chirp_rate * t
        # Phase: integral of 2*pi*f(t)*dt
-        _f_inst = f_if - chirp_bw / 2 + chirp_rate * t
+        f_inst = f_if - chirp_bw / 2 + chirp_rate * t
        phase = 2 * math.pi * (f_if - chirp_bw / 2) * t + math.pi * chirp_rate * t * t
        chirp_i.append(math.cos(phase))
        chirp_q.append(math.sin(phase))
@@ -163,7 +164,7 @@ def generate_if_chirp(n_samples, chirp_bw=CHIRP_BW, f_if=F_IF, fs=FS_ADC):
    return chirp_i, chirp_q


-def generate_reference_chirp_q15(n_fft=FFT_SIZE, chirp_bw=CHIRP_BW, _f_if=F_IF, _fs=FS_ADC):
+def generate_reference_chirp_q15(n_fft=FFT_SIZE, chirp_bw=CHIRP_BW, f_if=F_IF, fs=FS_ADC):
    """
    Generate a reference chirp in Q15 format for the matched filter.

@@ -190,8 +191,8 @@ def generate_reference_chirp_q15(n_fft=FFT_SIZE, chirp_bw=CHIRP_BW, _f_if=F_IF,
        # The beat frequency from a target at delay tau is: f_beat = chirp_rate * tau
        # Reference chirp is the TX chirp at baseband (zero delay)
        phase = math.pi * chirp_rate * t * t
-        re_val = round(32767 * 0.9 * math.cos(phase))
-        im_val = round(32767 * 0.9 * math.sin(phase))
+        re_val = int(round(32767 * 0.9 * math.cos(phase)))
+        im_val = int(round(32767 * 0.9 * math.sin(phase)))
        ref_re[n] = max(-32768, min(32767, re_val))
        ref_im[n] = max(-32768, min(32767, im_val))

@@ -284,7 +285,7 @@ def generate_adc_samples(targets, n_samples, noise_stddev=3.0,
    # Quantize to 8-bit unsigned (0-255), centered at 128
    adc_samples = []
    for val in adc_float:
-        quantized = round(val + 128)
+        quantized = int(round(val + 128))
        quantized = max(0, min(255, quantized))
        adc_samples.append(quantized)

@@ -346,8 +347,8 @@ def generate_baseband_samples(targets, n_samples_baseband, noise_stddev=0.5,
    bb_i = []
    bb_q = []
    for n in range(n_samples_baseband):
-        i_val = round(bb_i_float[n] + noise_stddev * rand_gaussian())
-        q_val = round(bb_q_float[n] + noise_stddev * rand_gaussian())
+        i_val = int(round(bb_i_float[n] + noise_stddev * rand_gaussian()))
+        q_val = int(round(bb_q_float[n] + noise_stddev * rand_gaussian()))
        bb_i.append(max(-32768, min(32767, i_val)))
        bb_q.append(max(-32768, min(32767, q_val)))

@@ -398,13 +399,15 @@ def generate_doppler_frame(targets, n_chirps=CHIRPS_PER_FRAME,
        for target in targets:
            # Which range bin does this target fall in?
            # After matched filter + range decimation:
+            # range_bin = target_delay_in_baseband_samples / decimation_factor
            delay_baseband_samples = target.delay_s * FS_SYS
            range_bin_float = delay_baseband_samples * n_range_bins / FFT_SIZE
-            range_bin = round(range_bin_float)
+            range_bin = int(round(range_bin_float))

            if range_bin < 0 or range_bin >= n_range_bins:
                continue

+            # Amplitude (simplified)
            amp = target.amplitude / 4.0

            # Doppler phase for this chirp.
@@ -424,7 +427,10 @@ def generate_doppler_frame(targets, n_chirps=CHIRPS_PER_FRAME,
                rb = range_bin + delta
                if 0 <= rb < n_range_bins:
                    # sinc-like weighting
-                    weight = 1.0 if delta == 0 else 0.2 / abs(delta)
+                    if delta == 0:
+                        weight = 1.0
+                    else:
+                        weight = 0.2 / abs(delta)
                    chirp_i[rb] += amp * weight * math.cos(total_phase)
                    chirp_q[rb] += amp * weight * math.sin(total_phase)

@@ -432,8 +438,8 @@ def generate_doppler_frame(targets, n_chirps=CHIRPS_PER_FRAME,
        row_i = []
        row_q = []
        for rb in range(n_range_bins):
-            i_val = round(chirp_i[rb] + noise_stddev * rand_gaussian())
-            q_val = round(chirp_q[rb] + noise_stddev * rand_gaussian())
+            i_val = int(round(chirp_i[rb] + noise_stddev * rand_gaussian()))
+            q_val = int(round(chirp_q[rb] + noise_stddev * rand_gaussian()))
            row_i.append(max(-32768, min(32767, i_val)))
            row_q.append(max(-32768, min(32767, q_val)))

@@ -461,7 +467,7 @@ def write_hex_file(filepath, samples, bits=8):

    with open(filepath, 'w') as f:
        f.write(f"// {len(samples)} samples, {bits}-bit, hex format for $readmemh\n")
-        for _i, s in enumerate(samples):
+        for i, s in enumerate(samples):
            if bits <= 8:
                val = s & 0xFF
            elif bits <= 16:
@@ -472,6 +478,7 @@ def write_hex_file(filepath, samples, bits=8):
                val = s & ((1 << bits) - 1)
            f.write(fmt.format(val) + "\n")

+    print(f"  Wrote {len(samples)} samples to {filepath}")


 def write_csv_file(filepath, columns, headers=None):
@@ -491,6 +498,7 @@ def write_csv_file(filepath, columns, headers=None):
            row = [str(col[i]) for col in columns]
            f.write(",".join(row) + "\n")

+    print(f"  Wrote {n_rows} rows to {filepath}")


 # =============================================================================
@@ -503,6 +511,10 @@ def scenario_single_target(range_m=500, velocity=0, rcs=0, n_adc_samples=16384):
    Good for validating matched filter range response.
    """
    target = Target(range_m=range_m, velocity_mps=velocity, rcs_dbsm=rcs)
+    print(f"Scenario: Single target at {range_m}m")
+    print(f"  {target}")
+    print(f"  Beat freq: {CHIRP_BW / T_LONG_CHIRP * target.delay_s:.0f} Hz")
+    print(f"  Delay: {target.delay_samples:.1f} ADC samples")

    adc = generate_adc_samples([target], n_adc_samples, noise_stddev=2.0)
    return adc, [target]
@@ -517,8 +529,9 @@ def scenario_two_targets(n_adc_samples=16384):
        Target(range_m=300, velocity_mps=0, rcs_dbsm=10, phase_deg=0),
        Target(range_m=315, velocity_mps=0, rcs_dbsm=10, phase_deg=45),
    ]
-    for _t in targets:
-        pass
+    print("Scenario: Two targets (range resolution test)")
+    for t in targets:
+        print(f"  {t}")

    adc = generate_adc_samples(targets, n_adc_samples, noise_stddev=2.0)
    return adc, targets
@@ -535,8 +548,9 @@ def scenario_multi_target(n_adc_samples=16384):
        Target(range_m=2000, velocity_mps=50, rcs_dbsm=0, phase_deg=45),
        Target(range_m=5000, velocity_mps=-5, rcs_dbsm=-5, phase_deg=270),
    ]
-    for _t in targets:
-        pass
+    print("Scenario: Multi-target (5 targets)")
+    for t in targets:
+        print(f"  {t}")

    adc = generate_adc_samples(targets, n_adc_samples, noise_stddev=3.0)
    return adc, targets
@@ -546,6 +560,7 @@ def scenario_noise_only(n_adc_samples=16384, noise_stddev=5.0):
    """
    Noise-only scene — baseline for false alarm characterization.
    """
+    print(f"Scenario: Noise only (stddev={noise_stddev})")
    adc = generate_adc_samples([], n_adc_samples, noise_stddev=noise_stddev)
    return adc, []

@@ -554,6 +569,7 @@ def scenario_dc_tone(n_adc_samples=16384, adc_value=128):
    """
    DC input — validates CIC decimation and DC response.
    """
+    print(f"Scenario: DC tone (ADC value={adc_value})")
    return [adc_value] * n_adc_samples, []


@@ -561,10 +577,11 @@ def scenario_sine_wave(n_adc_samples=16384, freq_hz=1e6, amplitude=50):
    """
    Pure sine wave at ADC input — validates NCO/mixer frequency response.
    """
+    print(f"Scenario: Sine wave at {freq_hz/1e6:.1f} MHz, amplitude={amplitude}")
    adc = []
    for n in range(n_adc_samples):
        t = n / FS_ADC
-        val = round(128 + amplitude * math.sin(2 * math.pi * freq_hz * t))
+        val = int(round(128 + amplitude * math.sin(2 * math.pi * freq_hz * t)))
        adc.append(max(0, min(255, val)))
    return adc, []

@@ -590,35 +607,46 @@ def generate_all_test_vectors(output_dir=None):
    if output_dir is None:
        output_dir = os.path.dirname(os.path.abspath(__file__))

+    print("=" * 60)
+    print("Generating AERIS-10 Test Vectors")
+    print(f"Output directory: {output_dir}")
+    print("=" * 60)

    n_adc = 16384  # ~41 us of ADC data

    # --- Scenario 1: Single target ---
+    print("\n--- Scenario 1: Single Target ---")
    adc1, targets1 = scenario_single_target(range_m=500, n_adc_samples=n_adc)
    write_hex_file(os.path.join(output_dir, "adc_single_target.hex"), adc1, bits=8)

    # --- Scenario 2: Multi-target ---
+    print("\n--- Scenario 2: Multi-Target ---")
    adc2, targets2 = scenario_multi_target(n_adc_samples=n_adc)
    write_hex_file(os.path.join(output_dir, "adc_multi_target.hex"), adc2, bits=8)

    # --- Scenario 3: Noise only ---
+    print("\n--- Scenario 3: Noise Only ---")
    adc3, _ = scenario_noise_only(n_adc_samples=n_adc)
    write_hex_file(os.path.join(output_dir, "adc_noise_only.hex"), adc3, bits=8)

    # --- Scenario 4: DC ---
+    print("\n--- Scenario 4: DC Input ---")
    adc4, _ = scenario_dc_tone(n_adc_samples=n_adc)
    write_hex_file(os.path.join(output_dir, "adc_dc.hex"), adc4, bits=8)

    # --- Scenario 5: Sine wave ---
+    print("\n--- Scenario 5: 1 MHz Sine ---")
    adc5, _ = scenario_sine_wave(n_adc_samples=n_adc, freq_hz=1e6, amplitude=50)
    write_hex_file(os.path.join(output_dir, "adc_sine_1mhz.hex"), adc5, bits=8)

    # --- Reference chirp for matched filter ---
+    print("\n--- Reference Chirp ---")
    ref_re, ref_im = generate_reference_chirp_q15()
    write_hex_file(os.path.join(output_dir, "ref_chirp_i.hex"), ref_re, bits=16)
    write_hex_file(os.path.join(output_dir, "ref_chirp_q.hex"), ref_im, bits=16)

    # --- Baseband samples for matched filter test (bypass DDC) ---
+    print("\n--- Baseband Samples (bypass DDC) ---")
    bb_targets = [
        Target(range_m=500, velocity_mps=0, rcs_dbsm=10),
        Target(range_m=1500, velocity_mps=20, rcs_dbsm=5),
@@ -628,6 +656,7 @@ def generate_all_test_vectors(output_dir=None):
    write_hex_file(os.path.join(output_dir, "bb_mf_test_q.hex"), bb_q, bits=16)

    # --- Scenario info CSV ---
+    print("\n--- Scenario Info ---")
    with open(os.path.join(output_dir, "scenario_info.txt"), 'w') as f:
        f.write("AERIS-10 Test Vector Scenarios\n")
        f.write("=" * 60 + "\n\n")
@@ -639,7 +668,7 @@ def generate_all_test_vectors(output_dir=None):
        f.write(f"  ADC: {FS_ADC/1e6:.0f} MSPS, {ADC_BITS}-bit\n")
        f.write(f"  Range resolution: {RANGE_RESOLUTION:.1f} m\n")
        f.write(f"  Wavelength: {WAVELENGTH*1000:.2f} mm\n")
-        f.write("\n")
+        f.write(f"\n")

        f.write("Scenario 1: Single target\n")
        for t in targets1:
@@ -657,7 +686,11 @@ def generate_all_test_vectors(output_dir=None):
        for t in bb_targets:
            f.write(f"  {t}\n")

+    print(f"\n  Wrote scenario info to {os.path.join(output_dir, 'scenario_info.txt')}")

+    print("\n" + "=" * 60)
+    print("ALL TEST VECTORS GENERATED")
+    print("=" * 60)

    return {
        'adc_single': adc1,
@@ -2,8 +2,8 @@
 """
 golden_reference.py — AERIS-10 FPGA bit-accurate golden reference model

-Uses ADI CN0566 Phaser radar data (10.525 GHz, used as test stimulus only) to
-validate the FPGA signal processing pipeline stage by stage:
+Uses ADI CN0566 Phaser radar data (10.525 GHz X-band FMCW) to validate
+the FPGA signal processing pipeline stage by stage:

    ADC → DDC (NCO+mixer+CIC+FIR) → Range FFT → Doppler FFT → Detection

@@ -20,6 +20,7 @@ Usage:

 import numpy as np
 import os
+import sys
 import argparse

 # ===========================================================================
@@ -69,6 +70,7 @@ FIR_COEFFS_HEX = [
 # DDC output interface
 DDC_OUT_BITS = 16                # 18 → 16 bit with rounding + saturation

+# FFT (Range)
 FFT_SIZE = 1024
 FFT_DATA_W = 16
 FFT_INTERNAL_W = 32
@@ -90,8 +92,7 @@ HAMMING_Q15 = [
    0x3088, 0x1B6D, 0x0E5C, 0x0A3D,
 ]

-# ADI dataset parameters — used ONLY for loading/requantizing ADI Phaser test data.
-# These are NOT PLFM hardware parameters. See AERIS-10 constants below.
+# ADI dataset parameters
 ADI_SAMPLE_RATE = 4e6            # 4 MSPS
 ADI_IF_FREQ = 100e3             # 100 kHz IF
 ADI_RF_FREQ = 9.9e9             # 9.9 GHz
@@ -100,17 +101,9 @@ ADI_RAMP_TIME = 300e-6          # 300 us
 ADI_NUM_CHIRPS = 256
 ADI_SAMPLES_PER_CHIRP = 1079

-# AERIS-10 hardware parameters (from ADF4382/AD9523/main.cpp configuration)
-AERIS_FS = 400e6                 # 400 MHz ADC clock (AD9523 OUT4)
-AERIS_IF = 120e6                 # 120 MHz IF (TX 10.5 GHz - RX 10.38 GHz)
-AERIS_FS_PROCESSING = 100e6     # Post-DDC rate (400 MSPS / 4x CIC)
-AERIS_CARRIER_HZ = 10.5e9       # TX LO (ADF4382, verified)
-AERIS_RX_LO_HZ = 10.38e9        # RX LO (ADF4382)
-AERIS_CHIRP_BW = 20e6           # Chirp bandwidth (target: 30 MHz Phase 1)
-AERIS_LONG_CHIRP_S = 30e-6      # Long chirp duration
-AERIS_PRI_S = 167e-6            # Pulse repetition interval
-AERIS_DECIMATION = 16           # Range bin decimation (1024 → 64)
-AERIS_RANGE_PER_BIN = 24.0      # Meters per decimated bin
+# AERIS-10 parameters
+AERIS_FS = 400e6                 # 400 MHz ADC clock
+AERIS_IF = 120e6                 # 120 MHz IF


 # ===========================================================================
@@ -156,15 +149,21 @@ def load_and_quantize_adi_data(data_path, config_path, frame_idx=0):
    4. Upconvert to 120 MHz IF (add I*cos - Q*sin) to create real signal
    5. Quantize to 8-bit unsigned (matching AD9484)
    """
+    print(f"[LOAD] Loading ADI dataset from {data_path}")
    data = np.load(data_path, allow_pickle=True)
    config = np.load(config_path, allow_pickle=True)
    
+    print(f"  Shape: {data.shape}, dtype: {data.dtype}")
+    print(f"  Config: sample_rate={config[0]:.0f}, IF={config[1]:.0f}, "
+          f"RF={config[2]:.0f}, chirps={config[3]:.0f}, BW={config[4]:.0f}, "
+          f"ramp={config[5]:.6f}s")
    
    # Extract one frame
    frame = data[frame_idx]  # (256, 1079) complex
    
    # Use first 32 chirps, first 1024 samples
    iq_block = frame[:DOPPLER_CHIRPS, :FFT_SIZE]  # (32, 1024) complex
+    print(f"  Using frame {frame_idx}: {DOPPLER_CHIRPS} chirps x {FFT_SIZE} samples")
    
    # The ADI data is baseband complex IQ at 4 MSPS.
    # AERIS-10 sees a real signal at 400 MSPS with 120 MHz IF.
@@ -199,6 +198,9 @@ def load_and_quantize_adi_data(data_path, config_path, frame_idx=0):
    iq_i = np.clip(iq_i, -32768, 32767)
    iq_q = np.clip(iq_q, -32768, 32767)
    
+    print(f"  Scaled to 16-bit (peak target {INPUT_PEAK_TARGET}): "
+          f"I range [{iq_i.min()}, {iq_i.max()}], "
+          f"Q range [{iq_q.min()}, {iq_q.max()}]")
    
    # Also create 8-bit ADC stimulus for DDC validation
    # Use just one chirp of real-valued data (I channel only, shifted to unsigned)
@@ -242,7 +244,10 @@ def nco_lookup(phase_accum, sin_lut):
    quadrant = (lut_address >> 6) & 0x3
    
    # Mirror index for odd quadrants
-    lut_idx = ~lut_address & 63 if quadrant & 1 ^ quadrant >> 1 & 1 else lut_address & 63
+    if (quadrant & 1) ^ ((quadrant >> 1) & 1):
+        lut_idx = (~lut_address) & 0x3F
+    else:
+        lut_idx = lut_address & 0x3F
    
    sin_abs = int(sin_lut[lut_idx])
    cos_abs = int(sin_lut[63 - lut_idx])
@@ -290,6 +295,7 @@ def run_ddc(adc_samples):
    # Build FIR coefficients as signed integers
    fir_coeffs = np.array([hex_to_signed(c, 18) for c in FIR_COEFFS_HEX], dtype=np.int64)
    
+    print(f"[DDC] Processing {n_samples} ADC samples at 400 MHz")
    
    # --- NCO + Mixer ---
    phase_accum = np.int64(0)
@@ -322,6 +328,7 @@ def run_ddc(adc_samples):
        # Phase accumulator update (ignore dithering for bit-accuracy)
        phase_accum = (phase_accum + NCO_PHASE_INC) & 0xFFFFFFFF
    
+    print(f"  Mixer output: I range [{mixed_i.min()}, {mixed_i.max()}]")
    
    # --- CIC Decimator (5-stage, decimate-by-4) ---
    # Integrator section (at 400 MHz rate)
@@ -329,9 +336,7 @@ def run_ddc(adc_samples):
    for n in range(n_samples):
        integrators[0][n + 1] = (integrators[0][n] + mixed_i[n]) & ((1 << CIC_ACC_WIDTH) - 1)
        for s in range(1, CIC_STAGES):
-            integrators[s][n + 1] = (
-                integrators[s][n] + integrators[s - 1][n + 1]
-            ) & ((1 << CIC_ACC_WIDTH) - 1)
+            integrators[s][n + 1] = (integrators[s][n] + integrators[s - 1][n + 1]) & ((1 << CIC_ACC_WIDTH) - 1)
    
    # Downsample by 4
    n_decimated = n_samples // CIC_DECIMATION
@@ -365,6 +370,7 @@ def run_ddc(adc_samples):
        scaled = comb[CIC_STAGES - 1][k] >> CIC_GAIN_SHIFT
        cic_output[k] = saturate(scaled, CIC_OUT_BITS)
    
+    print(f"  CIC output: {n_decimated} samples, range [{cic_output.min()}, {cic_output.max()}]")
    
    # --- FIR Filter (32-tap) ---
    delay_line = np.zeros(FIR_TAPS, dtype=np.int64)
@@ -386,6 +392,7 @@ def run_ddc(adc_samples):
        if fir_output[k] >= (1 << 17):
            fir_output[k] -= (1 << 18)
    
+    print(f"  FIR output: range [{fir_output.min()}, {fir_output.max()}]")
    
    # --- DDC Interface (18 → 16 bit) ---
    ddc_output = np.zeros(n_decimated, dtype=np.int64)
@@ -402,6 +409,7 @@ def run_ddc(adc_samples):
        else:
            ddc_output[k] = saturate(trunc + round_bit, 16)
    
+    print(f"  DDC output (16-bit): range [{ddc_output.min()}, {ddc_output.max()}]")
    
    return ddc_output

@@ -412,7 +420,7 @@ def run_ddc(adc_samples):
 def load_twiddle_rom(twiddle_file):
    """Load the quarter-wave cosine ROM from .mem file."""
    rom = []
-    with open(twiddle_file) as f:
+    with open(twiddle_file, 'r') as f:
        for line in f:
            line = line.strip()
            if not line or line.startswith('//'):
@@ -474,6 +482,7 @@ def run_range_fft(iq_i, iq_q, twiddle_file=None):
        # Generate twiddle factors if file not available
        cos_rom = np.round(32767 * np.cos(2 * np.pi * np.arange(N // 4) / N)).astype(np.int64)
    
+    print(f"[FFT] Running {N}-point range FFT (bit-accurate)")
    
    # Bit-reverse and sign-extend to 32-bit internal width
    def bit_reverse(val, bits):
@@ -511,6 +520,9 @@ def run_range_fft(iq_i, iq_q, twiddle_file=None):
            b_re = mem_re[addr_odd]
            b_im = mem_im[addr_odd]
            
+            # Twiddle multiply: forward FFT
+            #   prod_re = b_re * tw_cos + b_im * tw_sin
+            #   prod_im = b_im * tw_cos - b_re * tw_sin
            prod_re = b_re * tw_cos + b_im * tw_sin
            prod_im = b_im * tw_cos - b_re * tw_sin
            
@@ -533,6 +545,8 @@ def run_range_fft(iq_i, iq_q, twiddle_file=None):
        out_re[n] = saturate(mem_re[n], FFT_DATA_W)
        out_im[n] = saturate(mem_im[n], FFT_DATA_W)
    
+    print(f"  FFT output: re range [{out_re.min()}, {out_re.max()}], "
+          f"im range [{out_im.min()}, {out_im.max()}]")
    
    return out_re, out_im

@@ -567,6 +581,8 @@ def run_range_bin_decimator(range_fft_i, range_fft_q,
    decimated_i = np.zeros((n_chirps, output_bins), dtype=np.int64)
    decimated_q = np.zeros((n_chirps, output_bins), dtype=np.int64)

+    print(f"[DECIM] Decimating {n_in}→{output_bins} bins, mode={'peak' if mode==1 else 'avg' if mode==2 else 'simple'}, "
+          f"start_bin={start_bin}, {n_chirps} chirps")

    for c in range(n_chirps):
        # Index into input, skip start_bin
@@ -615,7 +631,7 @@ def run_range_bin_decimator(range_fft_i, range_fft_q,
                # Averaging: sum group, then >> 4 (divide by 16)
                sum_i = np.int64(0)
                sum_q = np.int64(0)
-                for _ in range(decimation_factor):
+                for s in range(decimation_factor):
                    if in_idx >= input_bins:
                        break
                    sum_i += int(range_fft_i[c, in_idx])
@@ -625,6 +641,9 @@ def run_range_bin_decimator(range_fft_i, range_fft_q,
                decimated_i[c, obin] = int(sum_i) >> 4
                decimated_q[c, obin] = int(sum_q) >> 4

+    print(f"  Decimated output: shape ({n_chirps}, {output_bins}), "
+          f"I range [{decimated_i.min()}, {decimated_i.max()}], "
+          f"Q range [{decimated_q.min()}, {decimated_q.max()}]")

    return decimated_i, decimated_q

@@ -650,6 +669,7 @@ def run_doppler_fft(range_data_i, range_data_q, twiddle_file_16=None):
    n_total = DOPPLER_TOTAL_BINS
    n_sf = CHIRPS_PER_SUBFRAME

+    print(f"[DOPPLER] Processing {n_range} range bins x {n_chirps} chirps → dual {n_fft}-point FFT")

    # Build 16-point Hamming window as signed 16-bit
    hamming = np.array([int(v) for v in HAMMING_Q15], dtype=np.int64)
@@ -659,9 +679,7 @@ def run_doppler_fft(range_data_i, range_data_q, twiddle_file_16=None):
    if twiddle_file_16 and os.path.exists(twiddle_file_16):
        cos_rom_16 = load_twiddle_rom(twiddle_file_16)
    else:
-        cos_rom_16 = np.round(
-            32767 * np.cos(2 * np.pi * np.arange(n_fft // 4) / n_fft)
-        ).astype(np.int64)
+        cos_rom_16 = np.round(32767 * np.cos(2 * np.pi * np.arange(n_fft // 4) / n_fft)).astype(np.int64)

    LOG2N_16 = 4
    doppler_map_i = np.zeros((n_range, n_total), dtype=np.int64)
@@ -733,6 +751,8 @@ def run_doppler_fft(range_data_i, range_data_q, twiddle_file_16=None):
                doppler_map_i[rbin, bin_offset + n] = saturate(mem_re[n], 16)
                doppler_map_q[rbin, bin_offset + n] = saturate(mem_im[n], 16)

+    print(f"  Doppler map: shape ({n_range}, {n_total}), "
+          f"I range [{doppler_map_i.min()}, {doppler_map_i.max()}]")

    return doppler_map_i, doppler_map_q

@@ -762,10 +782,12 @@ def run_mti_canceller(decim_i, decim_q, enable=True):
    mti_i = np.zeros_like(decim_i)
    mti_q = np.zeros_like(decim_q)

+    print(f"[MTI] 2-pulse canceller, enable={enable}, {n_chirps} chirps x {n_bins} bins")

    if not enable:
        mti_i[:] = decim_i
        mti_q[:] = decim_q
+        print(f"  Pass-through mode (MTI disabled)")
        return mti_i, mti_q

    for c in range(n_chirps):
@@ -781,6 +803,9 @@ def run_mti_canceller(decim_i, decim_q, enable=True):
                mti_i[c, r] = saturate(diff_i, 16)
                mti_q[c, r] = saturate(diff_q, 16)

+    print(f"  Chirp 0: muted (zeros)")
+    print(f"  Chirps 1-{n_chirps-1}: I range [{mti_i[1:].min()}, {mti_i[1:].max()}], "
+          f"Q range [{mti_q[1:].min()}, {mti_q[1:].max()}]")
    return mti_i, mti_q


@@ -807,12 +832,14 @@ def run_dc_notch(doppler_i, doppler_q, width=2):
      dc_notch_active = (width != 0) &&
                        (bin_within_sf < width || bin_within_sf > (15 - width + 1))
    """
-    _n_range, n_doppler = doppler_i.shape
+    n_range, n_doppler = doppler_i.shape
    notched_i = doppler_i.copy()
    notched_q = doppler_q.copy()

+    print(f"[DC NOTCH] width={width}, {n_range} range bins x {n_doppler} Doppler bins (dual sub-frame)")

    if width == 0:
+        print(f"  Pass-through (width=0)")
        return notched_i, notched_q

    zeroed_count = 0
@@ -824,6 +851,7 @@ def run_dc_notch(doppler_i, doppler_q, width=2):
            notched_q[:, dbin] = 0
            zeroed_count += 1

+    print(f"  Zeroed {zeroed_count} Doppler bin columns")
    return notched_i, notched_q


@@ -831,7 +859,7 @@ def run_dc_notch(doppler_i, doppler_q, width=2):
 # Stage 3e: CA-CFAR Detector (bit-accurate)
 # ===========================================================================
 def run_cfar_ca(doppler_i, doppler_q, guard=2, train=8,
-                alpha_q44=0x30, mode='CA', _simple_threshold=500):
+                alpha_q44=0x30, mode='CA', simple_threshold=500):
    """
    Bit-accurate model of cfar_ca.v — Cell-Averaging CFAR detector.

@@ -869,6 +897,9 @@ def run_cfar_ca(doppler_i, doppler_q, guard=2, train=8,
    if train == 0:
        train = 1

+    print(f"[CFAR] mode={mode}, guard={guard}, train={train}, "
+          f"alpha=0x{alpha_q44:02X} (Q4.4={alpha_q44/16:.2f}), "
+          f"{n_range} range x {n_doppler} Doppler")

    # Compute magnitudes: |I| + |Q| (17-bit unsigned, matching RTL L1 norm)
    # RTL: abs_i = I[15] ? (~I + 1) : I; abs_q = Q[15] ? (~Q + 1) : Q
@@ -936,19 +967,29 @@ def run_cfar_ca(doppler_i, doppler_q, guard=2, train=8,
            else:
                noise_sum = leading_sum + lagging_sum  # Default to CA

+            # Threshold = (alpha * noise_sum) >> ALPHA_FRAC_BITS
+            # RTL: noise_product = r_alpha * noise_sum_reg (31-bit)
+            #      threshold = noise_product[ALPHA_FRAC_BITS +: MAG_WIDTH]
+            #      saturate if overflow
            noise_product = alpha_q44 * noise_sum
            threshold_raw = noise_product >> ALPHA_FRAC_BITS

            # Saturate to MAG_WIDTH=17 bits
            MAX_MAG = (1 << 17) - 1  # 131071
-            threshold_val = MAX_MAG if threshold_raw > MAX_MAG else int(threshold_raw)
+            if threshold_raw > MAX_MAG:
+                threshold_val = MAX_MAG
+            else:
+                threshold_val = int(threshold_raw)

+            # Detection: magnitude > threshold
            if int(col[cut_idx]) > threshold_val:
                detect_flags[cut_idx, dbin] = True
                total_detections += 1

            thresholds[cut_idx, dbin] = threshold_val

+    print(f"  Total detections: {total_detections}")
+    print(f"  Magnitude range: [{magnitudes.min()}, {magnitudes.max()}]")

    return detect_flags, magnitudes, thresholds

@@ -962,16 +1003,19 @@ def run_detection(doppler_i, doppler_q, threshold=10000):
    cfar_mag = |I| + |Q| (17-bit)
    detection if cfar_mag > threshold
    """
+    print(f"[DETECT] Running magnitude threshold detection (threshold={threshold})")
    
    mag = np.abs(doppler_i) + np.abs(doppler_q)  # L1 norm (|I| + |Q|)
    detections = np.argwhere(mag > threshold)
    
+    print(f"  {len(detections)} detections found")
    for d in detections[:20]:  # Print first 20
        rbin, dbin = d
-        mag[rbin, dbin]
+        m = mag[rbin, dbin]
+        print(f"    Range bin {rbin}, Doppler bin {dbin}: magnitude {m}")
    
    if len(detections) > 20:
-        pass
+        print(f"    ... and {len(detections) - 20} more")
    
    return mag, detections

@@ -985,6 +1029,7 @@ def run_float_reference(iq_i, iq_q):
    Uses the exact same RTL Hamming window coefficients (Q15) to isolate
    only the FFT fixed-point quantization error.
    """
+    print(f"\n[FLOAT REF] Running floating-point reference pipeline")
    
    n_chirps, n_samples = iq_i.shape[0], iq_i.shape[1] if iq_i.ndim == 2 else len(iq_i)
    
@@ -1032,6 +1077,8 @@ def write_hex_files(output_dir, iq_i, iq_q, prefix="stim"):
                fi.write(signed_to_hex(int(iq_i[n]), 16) + '\n')
                fq.write(signed_to_hex(int(iq_q[n]), 16) + '\n')
        
+        print(f"  Wrote {fn_i} ({n_samples} samples)")
+        print(f"  Wrote {fn_q} ({n_samples} samples)")
    
    elif iq_i.ndim == 2:
        n_rows, n_cols = iq_i.shape
@@ -1045,6 +1092,8 @@ def write_hex_files(output_dir, iq_i, iq_q, prefix="stim"):
                    fi.write(signed_to_hex(int(iq_i[r, c]), 16) + '\n')
                    fq.write(signed_to_hex(int(iq_q[r, c]), 16) + '\n')
        
+        print(f"  Wrote {fn_i} ({n_rows}x{n_cols} = {n_rows * n_cols} samples)")
+        print(f"  Wrote {fn_q} ({n_rows}x{n_cols} = {n_rows * n_cols} samples)")


 def write_adc_hex(output_dir, adc_data, prefix="adc_stim"):
@@ -1056,12 +1105,13 @@ def write_adc_hex(output_dir, adc_data, prefix="adc_stim"):
        for n in range(len(adc_data)):
            f.write(format(int(adc_data[n]) & 0xFF, '02X') + '\n')
    
+    print(f"  Wrote {fn} ({len(adc_data)} samples)")


 # ===========================================================================
 # Comparison metrics
 # ===========================================================================
-def compare_outputs(_name, fixed_i, fixed_q, float_i, float_q):
+def compare_outputs(name, fixed_i, fixed_q, float_i, float_q):
    """Compare fixed-point outputs against floating-point reference.
    
    Reports two metrics:
@@ -1077,7 +1127,7 @@ def compare_outputs(_name, fixed_i, fixed_q, float_i, float_q):
    
    # Count saturated bins
    sat_mask = (np.abs(fi) >= 32767) | (np.abs(fq) >= 32767)
-    np.sum(sat_mask)
+    n_saturated = np.sum(sat_mask)
    
    # Complex error — overall
    fixed_complex = fi + 1j * fq
@@ -1086,8 +1136,8 @@ def compare_outputs(_name, fixed_i, fixed_q, float_i, float_q):
    
    signal_power = np.mean(np.abs(ref_complex) ** 2) + 1e-30
    noise_power = np.mean(np.abs(error) ** 2) + 1e-30
-    10 * np.log10(signal_power / noise_power)
-    np.max(np.abs(error))
+    snr_db = 10 * np.log10(signal_power / noise_power)
+    max_error = np.max(np.abs(error))
    
    # Non-saturated comparison
    non_sat = ~sat_mask
@@ -1096,10 +1146,17 @@ def compare_outputs(_name, fixed_i, fixed_q, float_i, float_q):
        sig_ns = np.mean(np.abs(ref_complex[non_sat]) ** 2) + 1e-30
        noise_ns = np.mean(np.abs(error_ns) ** 2) + 1e-30
        snr_ns = 10 * np.log10(sig_ns / noise_ns)
-        np.max(np.abs(error_ns))
+        max_err_ns = np.max(np.abs(error_ns))
    else:
        snr_ns = 0.0
+        max_err_ns = 0.0
    
+    print(f"\n  [{name}] Comparison ({n} points):")
+    print(f"    Saturated:           {n_saturated}/{n} ({100.0*n_saturated/n:.2f}%)")
+    print(f"    Overall SNR:         {snr_db:.1f} dB")
+    print(f"    Overall max error:   {max_error:.1f}")
+    print(f"    Non-sat SNR:         {snr_ns:.1f} dB")
+    print(f"    Non-sat max error:   {max_err_ns:.1f}")
    
    return snr_ns  # Return the meaningful metric

@@ -1111,12 +1168,7 @@ def main():
    parser = argparse.ArgumentParser(description="AERIS-10 FPGA golden reference model")
    parser.add_argument('--frame', type=int, default=0, help='Frame index to process')
    parser.add_argument('--plot', action='store_true', help='Show plots')
-    parser.add_argument(
-        '--threshold',
-        type=int,
-        default=10000,
-        help='Detection threshold (L1 magnitude)'
-    )
+    parser.add_argument('--threshold', type=int, default=10000, help='Detection threshold (L1 magnitude)')
    args = parser.parse_args()
    
    # Paths
@@ -1124,27 +1176,33 @@ def main():
    fpga_dir = os.path.abspath(os.path.join(script_dir, '..', '..', '..'))
    data_base = os.path.expanduser("~/Downloads/adi_radar_data")
    amp_data = os.path.join(data_base, "amp_radar", "phaser_amp_4MSPS_500M_300u_256_m3dB.npy")
-    amp_config = os.path.join(
-        data_base,
-        "amp_radar",
-        "phaser_amp_4MSPS_500M_300u_256_m3dB_config.npy"
-    )
+    amp_config = os.path.join(data_base, "amp_radar", "phaser_amp_4MSPS_500M_300u_256_m3dB_config.npy")
    twiddle_1024 = os.path.join(fpga_dir, "fft_twiddle_1024.mem")
    output_dir = os.path.join(script_dir, "hex")
    
+    print("=" * 72)
+    print("AERIS-10 FPGA Golden Reference Model")
+    print("Using ADI CN0566 Phaser Radar Data (10.525 GHz X-band FMCW)")
+    print("=" * 72)
    
    # -----------------------------------------------------------------------
    # Load and quantize ADI data
    # -----------------------------------------------------------------------
-    iq_i, iq_q, adc_8bit, _config = load_and_quantize_adi_data(
+    iq_i, iq_q, adc_8bit, config = load_and_quantize_adi_data(
        amp_data, amp_config, frame_idx=args.frame
    )
    
    # iq_i, iq_q: (32, 1024) int64, 16-bit range — post-DDC equivalent
+    print(f"\n{'=' * 72}")
+    print("Stage 0: Data loaded and quantized to 16-bit signed")
+    print(f"  IQ block shape: ({iq_i.shape[0]}, {iq_i.shape[1]})")
+    print(f"  ADC stimulus: {len(adc_8bit)} samples (8-bit unsigned)")
    
    # -----------------------------------------------------------------------
    # Write stimulus files
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Writing hex stimulus files for RTL testbenches")
    
    # Post-DDC IQ for each chirp (for FFT + Doppler validation)
    write_hex_files(output_dir, iq_i, iq_q, "post_ddc")
@@ -1158,6 +1216,8 @@ def main():
    # -----------------------------------------------------------------------
    # Run range FFT on first chirp (bit-accurate)
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Stage 2: Range FFT (1024-point, bit-accurate)")
    range_fft_i, range_fft_q = run_range_fft(iq_i[0], iq_q[0], twiddle_1024)
    write_hex_files(output_dir, range_fft_i, range_fft_q, "range_fft_chirp0")
    
@@ -1165,16 +1225,20 @@ def main():
    all_range_i = np.zeros((DOPPLER_CHIRPS, FFT_SIZE), dtype=np.int64)
    all_range_q = np.zeros((DOPPLER_CHIRPS, FFT_SIZE), dtype=np.int64)
    
+    print(f"\n  Running range FFT for all {DOPPLER_CHIRPS} chirps...")
    for c in range(DOPPLER_CHIRPS):
        ri, rq = run_range_fft(iq_i[c], iq_q[c], twiddle_1024)
        all_range_i[c] = ri
        all_range_q[c] = rq
        if (c + 1) % 8 == 0:
-            pass
+            print(f"    Chirp {c + 1}/{DOPPLER_CHIRPS} done")
    
    # -----------------------------------------------------------------------
    # Run Doppler FFT (bit-accurate) — "direct" path (first 64 bins)
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Stage 3: Doppler FFT (dual 16-point with Hamming window)")
+    print("  [direct path: first 64 range bins, no decimation]")
    twiddle_16 = os.path.join(fpga_dir, "fft_twiddle_16.mem")
    doppler_i, doppler_q = run_doppler_fft(all_range_i, all_range_q, twiddle_file_16=twiddle_16)
    write_hex_files(output_dir, doppler_i, doppler_q, "doppler_map")
@@ -1184,6 +1248,8 @@ def main():
    # This models the actual RTL data flow:
    #   range FFT → range_bin_decimator (peak detection) → Doppler
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Stage 2b: Range Bin Decimator (1024 → 64, peak detection)")
    
    decim_i, decim_q = run_range_bin_decimator(
        all_range_i, all_range_q,
@@ -1203,11 +1269,14 @@ def main():
                q_val = int(all_range_q[c, b]) & 0xFFFF
                packed = (q_val << 16) | i_val
                f.write(f"{packed:08X}\n")
+    print(f"  Wrote {fc_input_file} ({DOPPLER_CHIRPS * FFT_SIZE} packed IQ words)")
    
    # Write decimated output reference for standalone decimator test
    write_hex_files(output_dir, decim_i, decim_q, "decimated_range")
    
    # Now run Doppler on the decimated data — this is the full-chain reference
+    print(f"\n{'=' * 72}")
+    print("Stage 3b: Doppler FFT on decimated data (full-chain path)")
    fc_doppler_i, fc_doppler_q = run_doppler_fft(
        decim_i, decim_q, twiddle_file_16=twiddle_16
    )
@@ -1222,6 +1291,7 @@ def main():
                q_val = int(fc_doppler_q[rbin, dbin]) & 0xFFFF
                packed = (q_val << 16) | i_val
                f.write(f"{packed:08X}\n")
+    print(f"  Wrote {fc_doppler_packed_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} packed IQ words)")
    
    # Save numpy arrays for the full-chain path
    np.save(os.path.join(output_dir, "decimated_range_i.npy"), decim_i)
@@ -1234,12 +1304,16 @@ def main():
    # This models the complete RTL data flow:
    #   range FFT → decimator → MTI canceller → Doppler → DC notch → CFAR
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Stage 3c: MTI Canceller (2-pulse, on decimated data)")
    mti_i, mti_q = run_mti_canceller(decim_i, decim_q, enable=True)
    write_hex_files(output_dir, mti_i, mti_q, "fullchain_mti_ref")
    np.save(os.path.join(output_dir, "fullchain_mti_i.npy"), mti_i)
    np.save(os.path.join(output_dir, "fullchain_mti_q.npy"), mti_q)
    
    # Doppler on MTI-filtered data
+    print(f"\n{'=' * 72}")
+    print("Stage 3b+c: Doppler FFT on MTI-filtered decimated data")
    mti_doppler_i, mti_doppler_q = run_doppler_fft(
        mti_i, mti_q, twiddle_file_16=twiddle_16
    )
@@ -1249,6 +1323,8 @@ def main():
    
    # DC notch on MTI-Doppler data
    DC_NOTCH_WIDTH = 2  # Default test value: zero bins {0, 1, 31}
+    print(f"\n{'=' * 72}")
+    print(f"Stage 3d: DC Notch Filter (width={DC_NOTCH_WIDTH})")
    notched_i, notched_q = run_dc_notch(mti_doppler_i, mti_doppler_q, width=DC_NOTCH_WIDTH)
    write_hex_files(output_dir, notched_i, notched_q, "fullchain_notched_ref")
    
@@ -1261,12 +1337,15 @@ def main():
                q_val = int(notched_q[rbin, dbin]) & 0xFFFF
                packed = (q_val << 16) | i_val
                f.write(f"{packed:08X}\n")
+    print(f"  Wrote {fc_notched_packed_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} packed IQ words)")
    
    # CFAR on DC-notched data
    CFAR_GUARD = 2
    CFAR_TRAIN = 8
    CFAR_ALPHA = 0x30  # Q4.4 = 3.0
    CFAR_MODE = 'CA'
+    print(f"\n{'=' * 72}")
+    print(f"Stage 3e: CA-CFAR (guard={CFAR_GUARD}, train={CFAR_TRAIN}, alpha=0x{CFAR_ALPHA:02X})")
    cfar_flags, cfar_mag, cfar_thr = run_cfar_ca(
        notched_i, notched_q,
        guard=CFAR_GUARD, train=CFAR_TRAIN,
@@ -1281,6 +1360,7 @@ def main():
            for dbin in range(DOPPLER_TOTAL_BINS):
                m = int(cfar_mag[rbin, dbin]) & 0x1FFFF
                f.write(f"{m:05X}\n")
+    print(f"  Wrote {cfar_mag_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} mag values)")
    
    # 2. Threshold map (17-bit unsigned)
    cfar_thr_file = os.path.join(output_dir, "fullchain_cfar_thr.hex")
@@ -1289,6 +1369,7 @@ def main():
            for dbin in range(DOPPLER_TOTAL_BINS):
                t = int(cfar_thr[rbin, dbin]) & 0x1FFFF
                f.write(f"{t:05X}\n")
+    print(f"  Wrote {cfar_thr_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} threshold values)")
    
    # 3. Detection flags (1-bit per cell)
    cfar_det_file = os.path.join(output_dir, "fullchain_cfar_det.hex")
@@ -1297,21 +1378,20 @@ def main():
            for dbin in range(DOPPLER_TOTAL_BINS):
                d = 1 if cfar_flags[rbin, dbin] else 0
                f.write(f"{d:01X}\n")
+    print(f"  Wrote {cfar_det_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} detection flags)")
    
    # 4. Detection list (text)
    cfar_detections = np.argwhere(cfar_flags)
    cfar_det_list_file = os.path.join(output_dir, "fullchain_cfar_detections.txt")
    with open(cfar_det_list_file, 'w') as f:
-        f.write("# AERIS-10 Full-Chain CFAR Detection List\n")
+        f.write(f"# AERIS-10 Full-Chain CFAR Detection List\n")
        f.write(f"# Chain: decim -> MTI -> Doppler -> DC notch(w={DC_NOTCH_WIDTH}) -> CA-CFAR\n")
-        f.write(
-            f"# CFAR: guard={CFAR_GUARD}, train={CFAR_TRAIN}, "
-            f"alpha=0x{CFAR_ALPHA:02X}, mode={CFAR_MODE}\n"
-        )
-        f.write("# Format: range_bin doppler_bin magnitude threshold\n")
+        f.write(f"# CFAR: guard={CFAR_GUARD}, train={CFAR_TRAIN}, alpha=0x{CFAR_ALPHA:02X}, mode={CFAR_MODE}\n")
+        f.write(f"# Format: range_bin doppler_bin magnitude threshold\n")
        for det in cfar_detections:
            r, d = det
            f.write(f"{r} {d} {cfar_mag[r, d]} {cfar_thr[r, d]}\n")
+    print(f"  Wrote {cfar_det_list_file} ({len(cfar_detections)} detections)")
    
    # Save numpy arrays
    np.save(os.path.join(output_dir, "fullchain_cfar_mag.npy"), cfar_mag)
@@ -1319,17 +1399,20 @@ def main():
    np.save(os.path.join(output_dir, "fullchain_cfar_flags.npy"), cfar_flags)
    
    # Run detection on full-chain Doppler map
+    print(f"\n{'=' * 72}")
+    print("Stage 4: Detection on full-chain Doppler map")
    fc_mag, fc_detections = run_detection(fc_doppler_i, fc_doppler_q, threshold=args.threshold)
    
    # Save full-chain detection reference
    fc_det_file = os.path.join(output_dir, "fullchain_detections.txt")
    with open(fc_det_file, 'w') as f:
-        f.write("# AERIS-10 Full-Chain Golden Reference Detections\n")
+        f.write(f"# AERIS-10 Full-Chain Golden Reference Detections\n")
        f.write(f"# Threshold: {args.threshold}\n")
-        f.write("# Format: range_bin doppler_bin magnitude\n")
+        f.write(f"# Format: range_bin doppler_bin magnitude\n")
        for d in fc_detections:
            rbin, dbin = d
            f.write(f"{rbin} {dbin} {fc_mag[rbin, dbin]}\n")
+    print(f"  Wrote {fc_det_file} ({len(fc_detections)} detections)")
    
    # Also write detection reference as hex for RTL comparison
    fc_det_mag_file = os.path.join(output_dir, "fullchain_detection_mag.hex")
@@ -1338,38 +1421,44 @@ def main():
            for dbin in range(DOPPLER_TOTAL_BINS):
                m = int(fc_mag[rbin, dbin]) & 0x1FFFF  # 17-bit unsigned
                f.write(f"{m:05X}\n")
+    print(f"  Wrote {fc_det_mag_file} ({DOPPLER_RANGE_BINS * DOPPLER_TOTAL_BINS} magnitude values)")
    
    # -----------------------------------------------------------------------
    # Run detection on direct-path Doppler map (for backward compatibility)
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Stage 4b: Detection on direct-path Doppler map")
    mag, detections = run_detection(doppler_i, doppler_q, threshold=args.threshold)
    
    # Save detection list
    det_file = os.path.join(output_dir, "detections.txt")
    with open(det_file, 'w') as f:
-        f.write("# AERIS-10 Golden Reference Detections\n")
+        f.write(f"# AERIS-10 Golden Reference Detections\n")
        f.write(f"# Threshold: {args.threshold}\n")
-        f.write("# Format: range_bin doppler_bin magnitude\n")
+        f.write(f"# Format: range_bin doppler_bin magnitude\n")
        for d in detections:
            rbin, dbin = d
            f.write(f"{rbin} {dbin} {mag[rbin, dbin]}\n")
+    print(f"  Wrote {det_file} ({len(detections)} detections)")
    
    # -----------------------------------------------------------------------
    # Float reference and comparison
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("Comparison: Fixed-point vs Float reference")
    
    range_fft_float, doppler_float = run_float_reference(iq_i, iq_q)
    
    # Compare range FFT (chirp 0)
    float_range_i = np.real(range_fft_float[0, :]).astype(np.float64)
    float_range_q = np.imag(range_fft_float[0, :]).astype(np.float64)
-    compare_outputs("Range FFT", range_fft_i, range_fft_q,
+    snr_range = compare_outputs("Range FFT", range_fft_i, range_fft_q,
                                float_range_i, float_range_q)
    
    # Compare Doppler map
    float_doppler_i = np.real(doppler_float).flatten().astype(np.float64)
    float_doppler_q = np.imag(doppler_float).flatten().astype(np.float64)
-    compare_outputs("Doppler FFT", 
+    snr_doppler = compare_outputs("Doppler FFT", 
                                   doppler_i.flatten(), doppler_q.flatten(),
                                   float_doppler_i, float_doppler_q)
    
@@ -1381,10 +1470,26 @@ def main():
    np.save(os.path.join(output_dir, "doppler_map_i.npy"), doppler_i)
    np.save(os.path.join(output_dir, "doppler_map_q.npy"), doppler_q)
    np.save(os.path.join(output_dir, "detection_mag.npy"), mag)
+    print(f"\n  Saved numpy reference files to {output_dir}/")
    
    # -----------------------------------------------------------------------
    # Summary
    # -----------------------------------------------------------------------
+    print(f"\n{'=' * 72}")
+    print("SUMMARY")
+    print(f"{'=' * 72}")
+    print(f"  ADI dataset: frame {args.frame} of amp_radar (CN0566, 10.525 GHz)")
+    print(f"  Chirps processed: {DOPPLER_CHIRPS}")
+    print(f"  Samples/chirp: {FFT_SIZE}")
+    print(f"  Range FFT: {FFT_SIZE}-point → {snr_range:.1f} dB vs float")
+    print(f"  Doppler FFT (direct): {DOPPLER_FFT_SIZE}-point Hamming → {snr_doppler:.1f} dB vs float")
+    print(f"  Detections (direct): {len(detections)} (threshold={args.threshold})")
+    print(f"  Full-chain decimator: 1024→64 peak detection")
+    print(f"  Full-chain detections: {len(fc_detections)} (threshold={args.threshold})")
+    print(f"  MTI+CFAR chain: decim → MTI → Doppler → DC notch(w={DC_NOTCH_WIDTH}) → CA-CFAR")
+    print(f"  CFAR detections: {len(cfar_detections)} (guard={CFAR_GUARD}, train={CFAR_TRAIN}, alpha=0x{CFAR_ALPHA:02X})")
+    print(f"  Hex stimulus files: {output_dir}/")
+    print(f"  Ready for RTL co-simulation with Icarus Verilog")
    
    # -----------------------------------------------------------------------
    # Optional plots
@@ -1393,7 +1498,7 @@ def main():
        try:
            import matplotlib.pyplot as plt
            
-            _fig, axes = plt.subplots(2, 2, figsize=(14, 10))
+            fig, axes = plt.subplots(2, 2, figsize=(14, 10))
            
            # Range FFT magnitude (chirp 0)
            range_mag = np.sqrt(range_fft_i.astype(float)**2 + range_fft_q.astype(float)**2)
@@ -1435,10 +1540,11 @@ def main():
            plt.tight_layout()
            plot_file = os.path.join(output_dir, "golden_reference_plots.png")
            plt.savefig(plot_file, dpi=150)
+            print(f"\n  Saved plots to {plot_file}")
            plt.show()
            
        except ImportError:
-            pass
+            print("\n  [WARN] matplotlib not available, skipping plots")


 if __name__ == "__main__":
@@ -1,42 +0,0 @@
-# Golden Reference Hex Files
-
-These hex files are **committed golden references** for strict bit-exact
-real-data regression tests (`tb_doppler_realdata.v`, `tb_fullchain_realdata.v`).
-
-## When to regenerate
-
-Regenerate whenever the Doppler processing pipeline changes:
-
- `doppler_processor.v` (FFT size, window, sub-frame structure)
- `xfft_16.v` / `fft_engine.v` (butterfly arithmetic, twiddle lookup)
- `range_bin_decimator.v` (decimation mode, peak detection logic)
- `fft_twiddle_16.mem` (twiddle factor ROM)
-
-## How to regenerate
-
-```bash
-cd 9_Firmware/9_2_FPGA
-python3 tb/cosim/real_data/golden_reference.py
-# Then copy the Doppler-specific files:
-python3 -c "
-import numpy as np, os, shutil
-h = 'tb/cosim/real_data/hex'
-# Regenerate packed stimulus from range FFT npy
-ri = np.load(f'{h}/range_fft_all_i.npy')
-rq = np.load(f'{h}/range_fft_all_q.npy')
-with open(f'{h}/doppler_input_realdata.hex','w') as f:
-    for c in range(32):
-        for r in range(64):
-            i=int(ri[c,r])&0xFFFF; q=int(rq[c,r])&0xFFFF
-            f.write(f'{(q<<16)|i:08X}\n')
-shutil.copy2(f'{h}/doppler_map_i.hex', f'{h}/doppler_ref_i.hex')
-shutil.copy2(f'{h}/doppler_map_q.hex', f'{h}/doppler_ref_q.hex')
-"
-```
-
-## Architecture
-
-Generated against the **dual 16-point FFT** Doppler architecture
-(2 staggered-PRI sub-frames x 16-point Hamming-windowed FFT).
-
-Source data: ADI CN0566 Phaser radar (10.525 GHz X-band FMCW, 4 MSPS).
@@ -1,361 +1,291 @@
 # AERIS-10 Golden Reference Detections
 # Threshold: 10000
 # Format: range_bin doppler_bin magnitude
-0 0 35364
-0 1 16147
-0 15 11821
-0 16 24536
-0 17 11208
-0 31 10122
-1 0 25697
-1 1 12174
-1 15 13421
-1 16 20002
-1 17 11568
-1 31 11299
-2 0 16788
-2 16 20207
-2 31 10711
-3 0 29174
-3 1 13965
-3 15 13305
-3 16 31517
-3 17 13478
-3 31 14101
-4 0 41986
-4 1 19241
-4 15 21030
-4 16 39714
-4 17 17538
-4 31 20394
-5 0 23766
-5 1 11599
-5 15 14843
-5 16 18211
-5 31 12009
-6 0 42015
-6 1 21423
-6 15 21018
-6 16 47402
-6 17 22815
-6 31 22736
-7 0 32152
-7 1 15393
-7 15 14318
-7 16 28911
-7 17 13876
-7 31 17156
-8 0 11067
-10 0 18848
-10 15 10020
-10 16 20027
-10 31 10048
+0 0 44371
+0 1 24165
+0 31 17748
+1 0 34391
+1 1 17923
+1 31 18610
+2 0 28512
+2 1 13818
+2 31 15787
+3 0 47402
+3 1 25214
+3 31 23504
+4 0 51870
+4 1 32733
+4 31 31545
+5 0 31752
+5 1 13486
+5 31 19300
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+6 1 33383
+6 31 36672
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+8 0 14823
+10 0 30062
+10 1 13616
+10 31 17149
 11 0 65534
-11 1 37617
-11 2 14940
-11 15 43078
-11 16 65534
-11 17 39344
-11 31 45926
-12 0 58975
-12 1 22078
-12 15 34440
-12 16 59096
-12 17 22512
-12 31 28677
-13 0 38442
-13 1 29490
-13 15 37679
-13 16 44951
-13 17 27726
-13 31 39144
-14 0 52660
-14 1 27797
-14 2 13534
-14 15 39671
-14 16 57929
-14 17 24160
-14 31 31478
-15 0 30021
-15 1 12219
-15 15 17232
-15 16 29524
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-15 31 17850
-16 0 17593
-16 16 24710
-16 31 13046
-17 0 17606
-17 1 11119
-17 16 13182
-18 16 15914
-19 0 55785
-19 1 29069
-19 15 29418
-19 16 55308
-19 17 27886
-19 31 30649
-20 0 49230
-20 1 24486
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-20 16 45472
-20 17 21749
-20 31 21614
-21 0 26167
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-22 0 12791
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-25 1 40375
-25 15 54011
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-44 2 19166
-44 3 21321
-44 13 32864
-44 14 41461
-44 15 65535
-44 16 65535
-44 17 58493
-44 19 13967
-44 29 29756
-44 30 54069
+44 2 60795
+44 3 25438
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-45 1 58886
-45 14 22013
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-52 1 10467
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-52 16 21073
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-53 1 31121
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-53 16 44568
-53 17 28497
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-54 16 54060
-54 17 34252
-54 31 43616
-55 0 25597
-55 1 13662
-55 15 13184
-55 16 20525
-55 17 10363
-55 31 12295
-56 0 53620
-56 1 23575
-56 14 12578
-56 15 34783
-56 16 64499
-56 17 32442
-56 31 32139
+45 1 65535
+45 2 27652
+45 3 14416
+45 4 10622
+45 27 16323
+45 28 40935
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 # Chain: decim -> MTI -> Doppler -> DC notch(w=2) -> CA-CFAR
 # CFAR: guard=2, train=8, alpha=0x30, mode=CA
 # Format: range_bin doppler_bin magnitude threshold
-2 14 57128 48153
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--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Jason	765aa279ac	ci: add GitHub Actions workflow for full regression suite Three parallel jobs covering all AERIS-10 test infrastructure: - Python dashboard tests (58): protocol, connection, replay, opcodes, e2e - MCU firmware tests (20): bug regression (15) + Gap-3 safety (5) - FPGA regression (23 TBs + lint): unit, integration, and system e2e Triggers on push/PR to main and develop branches.	2026-04-07 23:09:12 +03:00
Jason	7326058fae	fix: remove server credentials from constraints README Accidentally included SSH key path, hostname, port, and internal server paths in the build quick-reference section. Replaced with generic instructions.	2026-04-07 21:37:24 +03:00
Jason	24a925d35a	docs: update constraints README with USB_MODE architecture and build guide Add USB Interface Architecture section documenting the USB_MODE parameter, generate block mechanism, per-target wrapper pattern, FT2232H pin map, and build quick-reference. Update top modules table (50T now uses radar_system_top_50t), bank voltage tables, and signal differences to reflect the FT2232H/FT601 dual-interface design.	2026-04-07 21:34:31 +03:00
Jason	a7051068b4	refactor(host): remove FT601 references from radar_dashboard, smoke_test, and docs Replace FT601Connection with FT2232HConnection in radar_dashboard.py and smoke_test.py. Both files had broken imports after FT601Connection was removed from radar_protocol.py. Also update requirements_dashboard.txt (ftd3xx -> pyftdi) and GUI_versions.txt descriptions.	2026-04-07 21:25:58 +03:00
Jason	0a09cb0658	test: update test_radar_dashboard for FT2232H-only protocol Align test suite with FT601 removal from radar_protocol.py: - Replace FT601Connection with FT2232HConnection throughout - Rewrite _make_data_packet() to build 11-byte packets (was 35-byte) - Update data packet roundtrip test for 11-byte format - Fix truncation test threshold (20 -> 6 bytes, since packets are 11) - Update ReplayConnection frame_len assertions (35 -> 11 per packet) 57 passed, 1 skipped (h5py), 0 failed.	2026-04-07 21:15:36 +03:00
Jason	b64209af4a	refactor(host): remove FT601 support from radar_protocol.py Strip all FT601/ftd3xx references from the core protocol module: - Remove FT601Connection class and ftd3xx import block - Remove _build_packets_ft601() 35-byte packet builder - Remove compact: bool parameter from RadarAcquisition - Remove dual-path parsing logic (compact vs FT601) - Rename parse_data_packet_compact -> parse_data_packet - Unify DATA_PACKET_SIZE to single 11-byte constant The 50T production board uses FT2232H exclusively. FT601 remains in out-of-scope legacy files (GUI_V6, etc).	2026-04-07 21:10:12 +03:00