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  • 0b170f7c61 Added Full Diagram NawfalMotii79 2026-03-20 00:22:45 +00:00
  • d7fc8c6771 Complete Diagram NawfalMotii79 2026-03-20 00:17:42 +00:00
  • 0745cc4f48 Pipeline CFAR noise computation: break critical path for timing closure Jason 2026-03-20 05:24:08 +02:00
  • f71923b67d Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS) Jason 2026-03-20 04:57:34 +02:00
  • e93bc33c6c Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS) Jason 2026-03-20 04:38:35 +02:00
  • 0b0643619c Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048 exact match Jason 2026-03-20 03:19:22 +02:00
  • b01c507de8 Added Full Diagram NawfalMotii79 2026-03-20 00:22:45 +00:00
  • 19284ac277 Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21 Jason 2026-03-20 02:21:33 +02:00
  • 836bf8fb9f Complete Diagram NawfalMotii79 2026-03-20 00:17:42 +00:00
  • 2efab23cd9 Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path Jason 2026-03-20 01:56:20 +02:00
  • 05efe692ad Add Build 21 TCL script for FFT opts + E2E RTL fixes Vivado build Jason 2026-03-20 01:48:51 +02:00
  • a31b4ec484 Update docs for FFT optimizations + E2E test + RTL fixes (19/19 FPGA regression) Jason 2026-03-20 01:46:24 +02:00
  • 0773001708 E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA) Jason 2026-03-20 01:45:00 +02:00
  • a3e1996833 FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index Jason 2026-03-20 00:20:59 +02:00
  • 02b3b68e00 Update docs for Gap 2 GUI Settings completion (5 of 7 gaps closed) Jason 2026-03-19 23:58:37 +02:00
  • 7cdfa486e5 Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU) Jason 2026-03-19 23:54:48 +02:00
  • d2f20f5c15 Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status Jason 2026-03-19 23:22:38 +02:00
  • e5d1b3cfc3 Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, add read path tests Jason 2026-03-19 23:16:26 +02:00
  • c6103b37de Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix Jason 2026-03-19 22:59:46 +02:00
  • f3bbf77ca1 Gap 3 Safety Architecture: IWDG watchdog, Emergency_Stop PA rail cutoff, temp max, periodic IDQ re-read, emergency state ordering + 5 tests (20/20 pass) Jason 2026-03-19 21:58:39 +02:00
  • c87dce0d41 Fix chirp memory loader BRAM async reset (Gap 5, REQP-1839/1840) Jason 2026-03-19 21:34:02 +02:00
  • 94ffdb8f77 Add Phase 0 Vivado-style lint to regression runner, update golden data Jason 2026-03-19 21:19:07 +02:00
  • e8b7cb7584 Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default Jason 2026-03-19 20:53:29 +02:00
  • 3b7afba9d9 Add Build 18 production script with report_exceptions fix for Vivado 2025.2 Jason 2026-03-19 20:40:32 +02:00
  • ed6f79c6d3 FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache Jason 2026-03-19 20:39:01 +02:00
  • 4e3c20066b Add Build 17 production build script with full 15-point analysis checklist Jason 2026-03-19 17:07:02 +02:00
  • 8ca6d992cb Update ILA probe script references from Build 13 to Build 16 Jason 2026-03-19 17:01:12 +02:00
  • 683e70e784 Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments Jason 2026-03-19 16:47:59 +02:00
  • e78e36a635 Add UART diagnostic capture tool for board-day bring-up Jason 2026-03-19 16:32:54 +02:00
  • 9b786eb33f Add FMC-path FT601 XDC for TE0713+TE0701+UMFT601X-B pin mapping Jason 2026-03-19 16:20:56 +02:00
  • f16d9524e5 Add board-day worksheet and cross-link bring-up docs Jason 2026-03-19 15:25:23 +02:00
  • 0009a74a49 Expand pre-hardware bring-up readiness docs Jason 2026-03-19 14:57:56 +02:00
  • e62f3cd950 Port validated Build 16 XDC cleanup and sync docs Jason 2026-03-19 14:34:26 +02:00
  • 2763b4be91 Fix CFAR blocking assignment (= to <=) in clocked block, add Build 15 analysis report Jason 2026-03-19 13:22:15 +02:00
  • 3fa26c9e4c Wire matched filter range profile to USB, replacing Doppler placeholder Jason 2026-03-19 12:33:40 +02:00
  • f4ff2715ca Fix matched filter golden test paths (40/40 pass, was 37/40) Jason 2026-03-19 12:20:37 +02:00
  • 463ebef554 CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner Jason 2026-03-19 11:31:46 +02:00
  • c466021bb6 Fix bugs B12-B17 (PA cal loop, ADC buffer, DIAG_SECTION args, htim3 init, stale annotations) with regression tests Jason 2026-03-19 11:04:53 +02:00
  • 49c9aa28ad Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining) Jason 2026-03-19 10:31:16 +02:00
  • 3b32f67087 Fix SPI bugs #9 (NULL platform_ops) and #10 (missing CS toggle), widen chip_select to uint16_t Jason 2026-03-19 10:00:05 +02:00
  • 397969348e Fix all 8 firmware bugs with regression tests Jason 2026-03-19 09:42:59 +02:00
  • b93ee04592 Add .gitignore for test build artifacts, remove committed binaries and .o files Jason 2026-03-19 09:28:48 +02:00
  • 28a66889ad Add MCU firmware test harness with 8 bug-confirming tests Jason 2026-03-19 09:28:19 +02:00
  • fda8aab7a2 Add DIAG instrumentation to beamformer, PA, USB, and remaining main.cpp subsystems Jason 2026-03-19 08:57:58 +02:00
  • bf912067cc Add bring-up diagnostic instrumentation to clocking/LO subsystem and main init Jason 2026-03-19 08:32:25 +02:00
  • 576fe71150 add contact info NawfalMotii79 2026-03-19 02:41:57 +00:00
  • b17e29e810 Add files via upload NawfalMotii79 2026-03-19 01:21:46 +00:00
  • b33a9bcd37 Add files via upload NawfalMotii79 2026-03-19 01:15:52 +00:00
  • ef0650b143 Add files via upload NawfalMotii79 2026-03-19 01:11:32 +00:00
  • 23672d6495 Add files via upload NawfalMotii79 2026-03-19 01:09:00 +00:00
  • 63abfaaa48 Add files via upload NawfalMotii79 2026-03-19 01:02:28 +00:00
  • 1231c7cc94 Add files via upload NawfalMotii79 2026-03-19 00:47:41 +00:00
  • b8d912658b Delete 2_Functional Diagram & Interconnection Matrices/Functional_Diagram.dwg NawfalMotii79 2026-03-18 23:31:18 +00:00
  • 981bd271fa Document repository file placement policy for generated artifacts Jason 2026-03-18 22:08:57 +02:00
  • bb7a7390c3 Clean gitignore after root artifact reorganization Jason 2026-03-18 22:08:02 +02:00
  • b879aefe6d Ignore local cleanup artifacts and generated report directories Jason 2026-03-18 22:04:44 +02:00
  • 3755ee6302 Publish Simulation Report v2 aligned to current FPGA baseline Jason 2026-03-18 21:51:08 +02:00
  • 5710f7a83e Annotate report currency status and flag legacy simulation PDF Jason 2026-03-18 21:46:52 +02:00
  • cad804c347 Add release notes page keyed to major bring-up commits Jason 2026-03-18 21:41:56 +02:00
  • 94eed1e933 Expand GitHub Pages into full engineering documentation site Jason 2026-03-18 21:40:44 +02:00
  • fcdd2708bb Add GitHub Pages docs site for antenna and simulation reports Jason 2026-03-18 21:34:26 +02:00
  • 967ce179eb Add TE0713/TE0701 alternate dev target for in-stock SoM path Jason 2026-03-18 15:01:55 +02:00
  • 25a739df07 Merge branch 'NawfalMotii79:main' into main Jason 2026-03-18 13:25:26 +02:00
  • eafa6c7555 removed a short detected by @Mamenace NawfalMotii79 2026-03-18 02:36:02 +00:00
  • 2453b16975 Add prepeg NawfalMotii79 2026-03-18 02:33:34 +00:00
  • 0ae7b40ff0 Add TE0712/TE0701 split target with dedicated top, XDC, and build flow Jason 2026-03-18 03:57:26 +02:00
  • 12e63b750c Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum Jason 2026-03-18 02:26:09 +02:00
  • f6877aab64 Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts Jason 2026-03-18 01:28:42 +02:00
  • 254c0e6f03 Improve timing margins with targeted datapath register tuning Jason 2026-03-17 23:51:04 +02:00
  • 36ad15247c Split fft_engine FSM: async reset for control, sync reset for DSP/BRAM datapath (Build 11) Jason 2026-03-17 21:40:09 +02:00
  • d8a8532097 Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10) Jason 2026-03-17 20:56:42 +02:00
  • 47606a4459 Rewrite integration testbench with golden self-reference comparison + physics bounds checks Jason 2026-03-17 20:56:28 +02:00
  • 1558f17d05 Convert async→sync reset on DSP/BRAM datapath registers for timing closure Jason 2026-03-17 20:11:13 +02:00
  • fcf3999e39 Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions Jason 2026-03-17 19:38:09 +02:00
  • 6fc5a10785 Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50. Jason 2026-03-17 15:40:55 +02:00
  • 37c8925df0 Merge branch 'NawfalMotii79:main' into main Jason 2026-03-17 13:59:12 +02:00
  • 5fd632bc47 Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator Jason 2026-03-17 13:48:47 +02:00
  • fb59e98737 Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs Jason 2026-03-17 12:47:22 +02:00
  • 0b52f49135 Added all boards stack NawfalMotii79 2026-03-17 02:26:23 +00:00
  • a9c857c447 Remove 15 dead files, move radar_system_tb.v to tb/ directory Jason 2026-03-17 01:08:12 +02:00
  • 66d4faa9c4 Merge branch 'NawfalMotii79:main' into main Jason 2026-03-17 00:45:42 +02:00
  • 91b9286d1b Add files via upload NawfalMotii79 2026-03-16 22:31:18 +00:00
  • 85e59d6f46 Added missing classes and functions NawfalMotii79 2026-03-16 22:25:10 +00:00
  • 6d27ab7217 Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization Jason 2026-03-16 23:23:06 +02:00
  • ffe36b42dc Fix NCO XSim test 12: add pipeline warmup and sample skip for 1 MHz zero-crossing test Jason 2026-03-16 23:21:25 +02:00
  • 49eb6169b6 Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB Jason 2026-03-16 23:17:38 +02:00
  • af1af3bb91 Fix XDC for timing closure: add hold waivers, remove stale constraints Jason 2026-03-16 23:04:16 +02:00
  • b823d83feb Add new testbenches and fix USB clock forwarding test Jason 2026-03-16 22:24:34 +02:00
  • 1acedf494c Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I Jason 2026-03-16 22:24:22 +02:00
  • fd6094ee9e Fix P0/P1 RTL bugs found during pre-hardware audit Jason 2026-03-16 22:24:06 +02:00
  • f154edbd20 Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001 Jason 2026-03-16 19:53:40 +02:00
  • 17b70bdcff Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment Jason 2026-03-16 19:15:23 +02:00
  • 39f78d4349 Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately Jason 2026-03-16 19:08:16 +02:00
  • 2db32af1d0 Add .mem file validator: verify FFT twiddle + chirp .mem files against radar parameters (55/56 PASS) Jason 2026-03-16 19:02:45 +02:00
  • e76925391c Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS) Jason 2026-03-16 18:51:08 +02:00
  • a5a5e96a57 Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale Jason 2026-03-16 18:14:06 +02:00
  • 17731dd482 Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites Jason 2026-03-16 18:09:26 +02:00
  • e506a80db5 Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0) Jason 2026-03-16 16:23:01 +02:00
  • baa24fd01e Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation Jason 2026-03-16 16:01:40 +02:00
  • 00fbab6c9d Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations) Jason 2026-03-16 15:02:35 +02:00